5 Strategic Decisions for Building a Scalable Compute Platform for Now and the Future
By Arm - 11 Feb, 2026 - Comments: 0

Artificial intelligence (AI) is no longer a “nice-to-have” technology—it’s a central driver of competitive advantage and business innovation. Across industries, enterprises are moving beyond experimentation and embedding AI into all their products, workflows, and customer experiences. But as organizations scale, many are discovering a stark reality: their compute infrastructure was not ... » read more

Optimal Surface Condition For Improved Cu-to-Cu Direct Bonding (NCHU, Osaka Univ.)
By Technical Paper Link - 10 Feb, 2026 - Comments: 0

A new technical paper titled "Hybrid surface pre-treatments for enhancing copper-to-copper direct bonding" was published by researchers at National Chung Hsing University (NCHU) and Osaka University. Abstract excerpt "Three-dimensional integrated circuits (3D IC) require low-temperature, high-reliability Cu–Cu direct bonding to support fine-pitch vertical interconnects and heterogeneous... » read more

Information Flow Verification Framework Integrating Static and Formal Verification Methods At The Pre-Silicon Stage (U. of Florida)
By Technical Paper Link - 10 Feb, 2026 - Comments: 0

Researchers from University of Florida published "IFV: Information Flow Verification at the Pre-silicon Stage Utilizing Static-Formal Methodology." Abstract "Modern system-on-chips (SoCs) are becoming prone to numerous security vulnerabilities due to their ever-growing complexity and size. Therefore, a comprehensive security verification framework is needed at the very early stage of the ... » read more

AFMTJ Model For In-Memory Computing (University of Arizona)
By Technical Paper Link - 10 Feb, 2026 - Comments: 0

University of Arizona researchers published "Antiferromagnetic Tunnel Junctions (AFMTJs) for In-Memory Computing: Modeling and Case Study." Abstract "Antiferromagnetic Tunnel Junctions (AFMTJs) enable picosecond switching and femtojoule writes through ultrafast sublattice dynamics. We present the first end-to-end AFMTJ simulation framework integrating multi-sublattice Landau-Lifshitz-Gilb... » read more

Catching Critical Defects In TSVs And Stacked Chips
By Laura Peters - 10 Feb, 2026 - Comments: 0

Key Takeaways Variation is becoming a bigger problem in multi-die assemblies with TSVs and hybrid bonding. Multi-modal approaches are required to test these devices. AI plays a role in improving defect capture rate and distinguishing between yield-killing and false positives. New methods for interconnecting devices using through-silicon vias (TSVs) and hybrid bonding in stac... » read more

Beyond Optical: A New E-Beam Inspection For Advanced Chips
By Christophe Begue - 10 Feb, 2026 - Comments: 0

The semiconductor industry is defined by its relentless pursuit of smaller, faster, and more powerful chips. As we push into advanced 3D architectures like gate-all-around (GAA) transistors, a critical challenge emerges: finding the defects that kill yield. Many of these flaws are deeply buried within complex structures and impossible to see with traditional optical inspection. This creates ... » read more

Resistance In Advanced Packages Is Now A System-Level Problem
By Gregory Haley - 10 Feb, 2026 - Comments: 0

Key Takeaways Kelvin measurement, which has been in use for decades, is no longer sufficient for addressing resistance in complex chips. The problem is that resistance is no longer concentrated in transistors, and where it does show up isn't always consistent or obvious. Traditional pass/fail approaches need to be replaced by more granular and flexible analytics and methodologies. ... » read more

Impact of the Gate and Fin Space Variation on Stress Modulation and FinFET Transistor Performance
By PDF Solutions - 10 Feb, 2026 - Comments: 0

Device scaling in advanced CMOS nodes is becoming more difficult due to patterning limitations and complex 3-D transistor integration schemes. This also makes the devices more sensitive to patterning variability. The presented study investigates the impact of poly pitch and fin pitch variability on stress-induced performance variation in 7nm FinFET transistors. Variations in critical dimension ... » read more

Are You Using Structural Patterns In An SLT Environment?
By Peter Orlando - 10 Feb, 2026 - Comments: 0

Extending the in‑field life of your silicon is essential for long‑term success and for staying ahead of your competitors in today’s rapidly evolving digital world of data centers, automotive and cellular chipsets, and AI applications. For those reasons, it’s increasingly important to test your silicon in a System Level Test (SLT) environment. Testing in an SLT environment offers many be... » read more

The Surface Metrology Decision Guide
By Bruker - 10 Feb, 2026 - Comments: 0

The Surface Metrology Decision Guide empowers readers to choose techniques and confidently engage with equipment providers. What’s inside: A side-by-side comparison of the resolution, strengths, and limitations of common surface metrology techniques An in-depth look at advances in and practical considerations for white-light interferometry (WLI) Summary chart of WLI objectives, ma... » read more

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