Chiplets Add More Inspection And Test Steps


Key Takeaways Ensuring the reliability of multi-die assemblies requires a variety of approaches to detect subsurface defects. Bonds and interconnects are especially problematic and require more inspection insertions. Ensuring reliability requires connecting fragmented data that is often siloed. The shift to multi-die assemblies is forcing changes in how chips are tested and ... » read more

Picosecond Ultrasonics: An Advanced Technology Utilized for Process Control of SiCr Thin Film Resistors


The bipolar-CMOS-DMOS (BCD) process is an advanced semiconductor technology integrating bipolar, CMOS, and DMOS devices onto a single chip, providing a compact, high-performance platform for the integration of analog, digital, and power circuitry. Thin-film resistors are employed to ensure precise resistance values and minimal temperature coefficients (TCR), thereby delivering enhanced accuracy... » read more

3D Printing To Create Spatially Freeform, Nanomaterial-based Electronics (Rice, U. of Utah, NUS)


Researchers from Rice University, University of Utah and National University of Singapore (NUS) published "Three-dimensional printing of nanomaterials-based electronics with a metamaterial-inspired near-field electromagnetic structure." Abstract "Three-dimensional (3D) printing can create freeform architectures and electronics with unprecedented versatility. However, the full potential of... » read more

Silicon Photonics In The Data Center: What A CMOS Exec Needs To Know


Silicon Photonics is changing the data center, with the biggest changes still ahead. Figure 1: Google Jupiter Network for multi-thousand Ironwood TPU clusters. Source: Google Refresher for new readers: Data centers contain hundreds or thousands of racks. For example, the Nvidia GB200 NVL72 AI compute/switch rack is about 24 inches wide, about 88 inches high and 42 inches deep. I... » read more

Chip Industry Technical Paper Roundup: Feb. 9


New technical papers recently added to Semiconductor Engineering’s library: [table id=521 /] Find more semiconductor research papers here. » read more

Research Bits: Feb. 9


Computing with heat Researchers from the Massachusetts Institute of Technology (MIT) designed silicon structures that can perform calculations in an electronic device using excess heat instead of electricity. The device was created using a software system that automatically designs a material that can conduct heat in a specific manner. The inverse design technique allowed the researchers to... » read more

Rutile TiO2 As A Post-ZrO2 Dielectric Platform for Next-Gen DRAM Capacitors (KIST)


Researchers at Korea Institute of Science and Technology (KIST) published "Beyond ZrO2: Rutile TiO2 as the Dielectric Platform for Next-Generation DRAM Capacitors." Abstract "As DRAM technology nodes move into the sub-10 nm regime, capacitor scaling is increasingly constrained by both footprint loss and a hard physical thickness limit for the entire electrode–dielectric–electrode stac... » read more

Thermal Characterization For Power Semiconductor Packages (KATECH)


Researchers from Korea Automotive Technology Institute published "Analytical Extraction of Thermal Resistance in Power Semiconductors Using Structural Function Derivatives and Series Resistance Modeling." Abstract "Junction-to-case thermal resistance (RthJC ) is a critical parameter for assessing the reliability and thermal performance of power semiconductor devices. Conventional JEDEC-ba... » read more

Overview of Interface Dipole Engineering: Formation Mechanisms, Control Methods, And Emerging Applications (SNU, Sejong U.)


Researchers at Seoul National University and Sejong University published "Interface dipole modulation for gate dielectrics in Field-Effect transistors: a review." Abstract "Interface dipole engineering has recently become a key technology in the fabrication of semiconductor FETs. This review comprehensively covers the principles, methods, and applications of interface dipoles in gate diel... » read more

Comprehensive System-Level Performance Model For p-SRAM-Based IMC (USC, UW-Madison)


Researchers at USC and University of Wisconsin-Madison published "System-Level Performance Modeling of Photonic In-Memory Computing." Abstract "Photonic in-memory computing is a high-speed, low-energy alternative to traditional transistor-based digital computing that utilizes high photonic operating frequencies and bandwidths. In this work, we develop a comprehensive system-level performa... » read more

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