Scalable quantum photonics; scheduling multicore architectures; HW triggered backdoors; performance model for photonic IMC; 300mm fab-compatible planar 2D FETs; thermal characterization power semiconductor packages; overview of Interface dipole engineering; next-gen DRAM capacitors.
New technical papers recently added to Semiconductor Engineering’s library:
| Technical Paper | Research Organizations |
|---|---|
| Foundry-Enabled Patterning of Diamond Quantum Microchiplets for Scalable Quantum Photonics | MIT, KAUST, PhotonFoundries and MITRE |
| Machine Learning for Energy-Performance-aware Scheduling | University of Cambridge |
| Beyond ZrO2: Rutile TiO2 as the Dielectric Platform for Next-Generation DRAM Capacitors | Korea Institute of Science and Technology |
| Hardware-Triggered Backdoors | BIFOLD, TU Berlin and CISPA |
| System-Level Performance Modeling of Photonic In-Memory Computing | USC and University of Wisconsin-Madison |
| Integration and electrical evaluation of WS2 and MoS2 fets in a 300 mm pilot line | Imec and KU Leuven |
| Analytical Extraction of Thermal Resistance in Power Semiconductors Using Structural Function Derivatives and Series Resistance Modeling | Korea Automotive Technology Institute |
| Interface dipole modulation for gate dielectrics in Field-Effect transistors: a review | Seoul National University and Sejong University |
Find more semiconductor research papers here.
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