Breaking The 2nm Barrier
By Mark LaPedus - 18 Feb, 2021 - Comments: 4

Chipmakers continue to make advancements with transistor technologies at the latest process nodes, but the interconnects within these structures are struggling to keep pace. The chip industry is working on several technologies to solve the interconnect bottleneck, but many of those solutions are still in R&D and may not appear for some time — possibly not until 2nm, which is expected t... » read more

FeFETs Bring Promise And Challenges
By Bryon Moyer - 17 Feb, 2021 - Comments: 3

Ferroelectric FETs (FeFETs) and memory (FeRAM) are generating high levels of interest in the research community. Based on a physical mechanism that hasn’t yet been commercially exploited, they join the other interesting new physics ideas that are in various stages of commercialization. “FeRAM is very promising, but it's like all promising memory technologies — it takes a while to get b... » read more

WLFO For High-Performance Low-Cost Packaging Of RFMEMS-CMOS
By Amkor - 17 Feb, 2021 - Comments: 0

Navigating the trade-offs between performance, size, cost and reliability can be a challenge when considering integrated circuit (IC) packaging and the end-application. The integration of micro-electromechanical systems (MEMS), either monolithic or heterogeneous, introduces yet another level of complexity that has only recently been a major focus of multi-device packaging. Wafer-level fanout (W... » read more

Marangoni Effect-Based Under-Layer For A Dual Damascene Via-First Approach
By Brewer Science - 17 Feb, 2021 - Comments: 0

One of the main challenges of a Dual Damascene (DD) via-first process is the control of the Critical Dimensions (CDs) in the lithography of the trenches. The PhotoResist (PhR) thickness presents variations from the via arrays to the open areas, which cause the variation of CDs: the swing effect. The planarization of a DD via-first process is reported. A dual-layer solution is used to demonstrat... » read more

Evaluation Of The Impact Of Source Drain epi Implementation On Logic Performance Using Combined Process And Circuit Simulation
By Coventor - 17 Feb, 2021 - Comments: 0

In this paper, we explore an end-to-end solution using SEMulator3D to address the need to include process variation effects in circuit simulation. For the first time, we couple SEMulator3D with BSIM compact modeling to evaluate process variation impacts on circuit performance. The process integration goal of the study was to optimize contacts and spacer thickness of advanced-node FinFETs in ter... » read more

Blog Review: Feb. 17
By Jesse Allen - 17 Feb, 2021 - Comments: 0

In a video, Synopsys' Tim Mackey warns that IoT device manufacturers are dealing with a serious challenge when it comes to security and points to the types of software threats that could impact IoT products. Siemens' Paul van Straten finds that the rise in vehicle complexity and intensified global competition means traditional automotive OEMs will need to explore new approaches to vehicle de... » read more

Securing ICs With Information Flow Analysis
By Ed Sperling - 16 Feb, 2021 - Comments: 0

Following the data has new meaning when it comes to security. Alric Althoff, senior hardware security engineer at Tortuga Logic, talks about tracking the flow of data through a hardware design over time, including what happens with roots of trust, how this works with existing tools and methodologies, and what to think about when tracing potential security risks. » read more

Manufacturing Bits: Feb. 16
By Mark LaPedus - 16 Feb, 2021 - Comments: 0

Hybrid bonding consortium for packaging A*STAR’s Institute of Microelectronics (IME) and several companies have formed a new consortium to propel the development of hybrid bonding technology for chip-packaging applications. The group, called the Chip-to-Wafer (C2W) Hybrid Bonding Consortium, includes A*STAR’s IME organization, Applied Materials, ASM Pacific, Capcon, HD MicroSystems, ONT... » read more

Power/Performance Bits: Feb. 16
By Jesse Allen - 16 Feb, 2021 - Comments: 0

Superconducting microprocessor Researchers at Yokohama National University created a superconducting processor with zero electrical resistance. Huge amounts of power are being used by computers today, and compared to the human brain, they are many orders of magnitude less efficient. Superconductors have been a popular approach to making computers more efficient, but this requires extreme co... » read more

Single Chip Auto-Valet Parking System with TDA4VMID SoC
By Technical Paper Link - 15 Feb, 2021 - Comments: 0

Abstract "Auto-Valet parking is a key emerging function for Advanced Driver Assistance Systems (ADAS) enhancing traditional surround view system providing more autonomy during parking scenario. Auto-Valet parking system is typically built using multiple HW components e.g. ISP, micro-controllers, FPGAs, GPU, Ethernet/PCIe switch etc. Texas Instrument’s new Jacinto7 platform is one of industry... » read more

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