Research Bits: March 1


Large-scale phased array Researchers at Princeton University developed a large-scale high-frequency antenna array using thin-film materials. “To achieve these large dimensions, people have tried discrete integration of hundreds of little microchips. But that’s not practical — it’s not low-cost, it’s not reliable, it’s not scalable on a wireless systems level,” said senior stud... » read more

2D Semiconductors Make Progress, But Slowly


Researchers are looking at a variety of new materials at future nodes, but progress remains slow. In recent years, 2D semiconductors have emerged as a leading potential solution to the problem of channel control in highly scaled transistors. As devices shrink, the channel thickness should shrink proportionally. Otherwise, the gate capacitance won’t be large enough to control the flow of cu... » read more

Week In Review: Manufacturing, Test


Chipmakers, OEMs UMC plans to build a new fab next to its existing 300mm fab in Singapore. The new fab, called Fab12i P3, will manufacture wafers based on UMC’s 22nm/28nm processes. The planned investment for this project will be $5 billion. The first phase of this greenfield fab will have a monthly capacity of 30,000 wafers with production expected to commence in late 2024. To account fo... » read more

Week In Review: Design, Low Power


Tools & IP Codasip debuted two new customizable low power embedded RISC-V processor cores. To support embedded AI applications, the L31/L11 cores run Google’s TensorFlowLite for Microcontrollers. Codasip Studio tools can be used to customize for specific system, software, and application requirements. Licensing the CodAL description of a Codasip RISC-V core grants customers a full archit... » read more

Week In Review: Auto, Security, Pervasive Computing


Security Fraunhofer IIS received a grant to establish an R&D center for trustworthy integrated electronic systems for security and safety. Working with other Fraunhofer divisions, Fraunhofer IIS will use innovative methods in design and testing to help protect IP along the value chain of microelectronic components and systems. The center will focus on creating a secure design flow for inte... » read more

Data Center Architectures In Flux


Data center architectures are becoming increasingly customized and heterogeneous, shifting from processors made by a single vendor to a mix of processors and accelerators made by multiple vendors — including system companies' own design teams. Hyperscaler data centers have been migrating toward increasingly heterogeneous architectures for the past half decade or so, spurred by the rising c... » read more

Why RISC-V Is Succeeding


There is no disputing the excitement surround the introduction of the RISC-V processor architecture. Yet while many have called it a harbinger of a much broader open-source hardware movement, the reasons behind its success are not obvious, and the implications for an expansion of more open-source cores is far from certain. “The adoption of RISC-V as the preferred architecture for many sili... » read more

Unintended Coupling Issues Grow


The number of indirect and often unexpected ways in which one design element may be affected by another is growing, making it more difficult to ensure a chip — or multiple chips in a package — will perform reliably. Long gone are the days when the only way that one part of a circuit could influence another was by an intended wire connecting them. As geometries get smaller, frequencies go... » read more

Does EDA Sell Fear?


I worked in the EDA industry for over 30 years and a common lament I heard was that the EDA industry survived by selling fear. Your new chip will fail if you do not buy the latest tool offering. There always seemed to be a natural dislike for the EDA industry and many users thought the industry overcharged and was unable to innovate. I never quite understood the reasoning. A recent comment, ... » read more

Dissolving The Barriers In Multi-Substrate 3D-IC Assembly Design


Advanced packaging continues to promise improved form factor, cost, performance, and functionality compared to the traditional transistor scaling on SoCs. This is done by integrating multiple dies on top of a substrate (organic or silicon). Besides multiple dies, multiple substrates can typically exist in a 3D-IC assembly. In this case, the benefits of advanced packaging are taken to a whole ne... » read more

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