Manufacturing Bits: Aug. 24

By Mark LaPedus - 24 Aug, 2021 - Comments: 0

Panel packaging consortium Fraunhofer Institute for Reliability and Microintegration IZM has provided an update on a consortium that is developing panel-level IC packaging technologies. Fraunhofer IZM is leading the consortium. The R&D organization and its partners, including Intel and others, have made progress in terms of equipment, processes and other technologies in the so-called Pa... » read more

Power/Performance Bits: Aug. 24

By Jesse Allen - 24 Aug, 2021 - Comments: 0

Low power AI Engineers at the Swiss Center for Electronics and Microtechnology (CSEM) designed an SoC for edge AI applications that can run on solar power or a small battery. The SoC consists of an ASIC chip with RISC-V processor developed at CSEM along with two tightly coupled machine-learning accelerators: one for face detection, for example, and one for classification. The first is a bin... » read more

Inside Intel’s Ambitious Roadmap

By Mark LaPedus and Ed Sperling - 23 Aug, 2021 - Comments: 2

Ann Kelleher, senior vice president and general manager of Technology Development at Intel, sat down with Semiconductor Engineering to talk about the company’s new logic roadmap, as well as lithography, packaging, and process technology. What follows are excerpts of that discussion. SE: Intel recently disclosed its new logic roadmap. Beyond Intel 3, the company is working on Intel 20A. Wit... » read more

2D materials–based homogeneous transistor-memory architecture for neuromorphic hardware

By Technical Paper Link - 21 Aug, 2021 - Comments: 0

Abstract "In neuromorphic hardware, peripheral circuits and memories based on heterogeneous devices are generally physically separated. Thus exploring homogeneous devices for these components is an important issue for improving module integration and resistance matching. Inspired by ferroelectric proximity effect on two-dimensional materials, we present a tungsten diselenide-on-LiNbO3 cascaded... » read more

Week In Review: Manufacturing, Test

By Mark LaPedus - 20 Aug, 2021 - Comments: 0

Chipmakers, OEMs At Intel’s Architecture Day this week, the company revealed several new chip architectures. Some were already announced, while others are new. These include Intel’s first performance hybrid architecture, a data center architecture, a discrete gaming graphics processing unit (GPU) architecture, infrastructure processing units (IPUs), and a data center GPU architecture. Here... » read more

Week In Review: Design, Low Power

By Jesse Allen - 20 Aug, 2021 - Comments: 0

Tools Cadence teamed up with Tower Semiconductor to release a silicon-validated SP4T RF SOI switch reference design flow using the Cadence Virtuoso Design Platform and RF Solution. The reference design flow targets advanced 5G wireless, wireline infrastructure, and automotive IC product development and include a set of mixed-signal and RF design, simulation, system analysis and signoff tools t... » read more

Week In Review: Auto, Security, Pervasive Computing

By SE Staff - 20 Aug, 2021 - Comments: 0

Security Infineon Technologies is coordinating a group of twelve partners, including researchers, electronics industry, and end users, who are working to find and fix IoT security flaws. The research project, called “Design methods and hardware/software co-verification for the unique identifiability of electronic components” falls under VE-VIDES, which is part of the Trustworthy Electronic... » read more

FORMS: Fine-grained Polarized ReRAM-based In-situ Computation for Mixed-signal DNN Accelerator

By Technical Paper Link - 19 Aug, 2021 - Comments: 0

Abstract: "Recent work demonstrated the promise of using resistive random access memory (ReRAM) as an emerging technology to perform inherently parallel analog domain in-situ matrix-vector multiplication—the intensive and key computation in deep neural networks (DNNs). One key problem is the weights that are signed values. However, in a ReRAM crossbar, weights are stored as conductance of... » read more

Vector Runahead

By Technical Paper Link - 19 Aug, 2021 - Comments: 0

Abstract: "The memory wall places a significant limit on performance for many modern workloads. These applications feature complex chains of dependent, indirect memory accesses, which cannot be picked up by even the most advanced microarchitectural prefetchers. The result is that current out-of-order superscalar processors spend the majority of their time stalled. While it is possible to bui... » read more

Hardware Architecture and Software Stack for PIM Based on Commercial DRAM Technology

By Technical Paper Link - 19 Aug, 2021 - Comments: 0

Abstract: "Emerging applications such as deep neural network demand high off-chip memory bandwidth. However, under stringent physical constraints of chip packages and system boards, it becomes very expensive to further increase the bandwidth of off-chip memory. Besides, transferring data across the memory hierarchy constitutes a large fraction of total energy consumption of systems, and the ... » read more

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