Research Bits: Nov. 4
By Jesse Allen - 04 Nov, 2025 - Comments: 0

Diffusive memristor for artificial neurons Researchers from the University of Southern California, University of Massachusetts, University of California Los Angeles, Syracuse University, and the Air Force Research Laboratory developed artificial neurons that replicate the complex electrochemical behavior of biological brain cells. “Our existing computing systems were never intended to pro... » read more

Co-Simulation Framework for Parallel DNN Execution on Chiplet-Based Systems (UW–Madison, Washington State)
By Technical Paper Link - 03 Nov, 2025 - Comments: 0

A new technical paper titled "CHIPSIM: A Co-Simulation Framework for Deep Learning on Chiplet-Based Systems" was published by researchers at University of Wisconsin–Madison and Washington State University. Abstract "Due to reduced manufacturing yields, traditional monolithic chips cannot keep up with the compute, memory, and communication demands of data-intensive applications, such as ra... » read more

Emergence Of The JJFET For Cryogenic and Quantum-Compatible Logic (Univ. of Glasgow)
By Technical Paper Link - 03 Nov, 2025 - Comments: 0

A new technical paper titled "Silicon-based Josephson junction field-effect transistors enabling cryogenic logic and quantum technologies" was published by researchers at University of Glasgow. Abstract "The continuous miniaturisation of metal-oxide-semiconductor field-effect transistors (MOSFETs) from long- to short-channel architectures has advanced beyond the predictions of Moore's Law. ... » read more

LPDDR6: Not Just For Mobile Anymore
By Ed Sperling - 03 Nov, 2025 - Comments: 0

LPDDR memory has been almost synonymous with mobile devices, but starting with the new LPDDR6 specification released in July 2025 by JEDEC, it will begin showing up inside of data centers, as well, early next year. The key factors in various flavors of DRAM are bandwidth, capacity, and cost. HBM is the fastest, but it's also expensive, and it requires a 2.5D or 3.5D packaging approach. GDDR is ... » read more

The Next Big Thing
By Brian Bailey - 03 Nov, 2025 - Comments: 0

Sometimes, we spend so much time looking for the next big thing that we actually miss something even bigger. I have to admit I was guilty of this while employed by a large EDA company 20 years ago. I was one of those ESL people — Electronic System Level acolytes, with Gary Smith as our standard bearer. We wanted to do many things, including raising the level of abstraction for design and veri... » read more

Small Vs. Large Language Models
By Ed Sperling - 03 Nov, 2025 - Comments: 0

The proliferation of edge AI will require fundamental changes in language models and chip architectures to make inferencing and learning outside of AI data centers a viable option. The initial goal for small language models (SLMs) — roughly 10 billion parameters or less, compared to more than a trillion parameters in the biggest LLMs — was to leverage them exclusively for inferencing. In... » read more

MIT’s Survey On Accelerators and Processors for Inference, With Peak Performance And Power Comparisons
By Technical Paper Link - 31 Oct, 2025 - Comments: 0

A new technical paper titled "Lincoln AI Computing Survey (LAICS) and Trends" was published by researchers at MIT Lincoln Laboratory Supercomputing Center. Abstract "In the past year, generative AI (GenAI) models have received a tremendous amount of attention, which in turn has increased attention to computing systems for training and inference for GenAI. Hence, an update to this survey is ... » read more

SOT-Based MRAM Design At 7nm (Georgia Tech, Intel)
By Technical Paper Link - 31 Oct, 2025 - Comments: 0

A new technical paper titled "Comprehensive device to system co-design for SOT-MRAM at the 7nm node" was published by researchers at Georgia Institute of Technology and Intel. Abstract "This work presents a comprehensive spin-orbit torque (SOT) based random access memory (MRAM) design at the 7nm technology node, spanning from device-level characteristics to system-level power performance ar... » read more

In-DRAM TRNG Using Simultaneous Multiple-Row Activation (ETH Zurich, CISPA)
By Technical Paper Link - 31 Oct, 2025 - Comments: 0

A new technical paper titled "In-DRAM True Random Number Generation Using Simultaneous Multiple-Row Activation: An Experimental Study of Real DRAM Chips" was published by researchers at ETH Zürich and CISPA. Abstract "In this work, we experimentally demonstrate that it is possible to generate true random numbers at high throughput and low latency in commercial off-the-shelf (COTS) DRAM chi... » read more

Chip Industry Week in Review
By The SE Staff - 31 Oct, 2025 - Comments: 0

San Francisco-based Substrate raised more than $100 million to build a vertically integrated foundry that uses particle accelerators to produce "the world's brightest beams, enabling a new method of advanced X-ray lithography." The company claims its technology is comparable to ASML's high NA EUV, and notes it can extend well beyond 2nm. ASML has not publicly commented. The Nexperia chip sho... » read more

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