Utilizing Chiplet-Locality For Efficient Memory Mapping In MCM GPUs (ETRI, Sungkyunkwan Univ.)
By Technical Paper Link - 30 Oct, 2025 - Comments: 0

A new technical paper titled "Leveraging Chiplet-Locality for Efficient Memory Mapping in Multi-Chip Module GPUs" was published by researchers at Electronics and Telecommunications Research Institute (ETRI) and Sungkyunkwan University. Abstract "While the multi-chip module (MCM) design allows GPUs to scale compute and memory capabilities through multi-chip integration, it introduces memory ... » read more

Smart Handling Of Reset Domain Crossings To Non-Resettable Flip-Flops
By Reetika - 30 Oct, 2025 - Comments: 0

As system-on-chip (SoC) designs evolve, they aren’t just getting bigger — they’re becoming more intricate. One of the trickiest challenges in this evolution lies in handling resets. Today’s architectures often juggle multiple asynchronous reset sources alongside sequential elements such as non-resettable registers (NRRs), which operate without dedicated reset pins. When a signal crosses... » read more

Top Five Trends In RTL Signoff
By Suresh Babu Barla - 30 Oct, 2025 - Comments: 0

By Suresh Babu Barla and Rimpy Chugh The “shift left” of the development cycle is critical for the huge, complex chips used in such applications as AI and high-performance computing (HPC). Identifying design issues at the netlist stage occurs far too late in the design development process. At this point, addressing such problems demands significant effort, primarily because most design-r... » read more

Thermal, Mechanical, And Material Stresses Grow With Die Stacking
By Ann Mutschler - 30 Oct, 2025 - Comments: 0

Managing thermal and mechanical stress in multi-die assemblies will require a detailed knowledge of how and where a device will be used, how it will be packaged, and where stresses could cause problems at any point during its expected lifetime. This includes everything from workload-dependent thermal gradients to mechanical and electrical stress, which may become more pronounced over time wi... » read more

Efficiency Defines The Future Of Data Movement
By Andy Nightingale - 30 Oct, 2025 - Comments: 0

For decades, chip performance was measured by how much raw compute could be packed onto a die. However, that equation has changed. Moving data across a system-on-chip (SoC) now consumes more energy than the computations it performs. Efficient data movement has become a significant challenge for next-generation SoC designs. AI workloads are multiplying, hyperscale data centers are approaching po... » read more

Even With AI Inroads, Human Chip Designers Still Essential
By Liz Allan - 30 Oct, 2025 - Comments: 0

The proliferation of AI tools seems perfectly matched to fill a talent shortage, but a closer look shows the skills do not entirely overlap. Certain parts of the EDA pipeline require human engineers, and it seems likely to stay that way for the foreseeable future. The dark art of analog design, the final word on safety-critical functional safety, high-level architectural decisions, product i... » read more

Enhancing PCIe 6.0 Performance: Flit Sequence Numbers And Selective NAK Explained
By Felipe Gonçalves - 30 Oct, 2025 - Comments: 0

The Flit Sequence Number is a mechanism introduced in the PCIe 6.0 specification, accompanying the transition to Flit Mode operation. This enhancement supersedes the legacy transaction layer packet (TLP) sequence numbering, along with its associated acknowledgment and replay protocols. What is a Flit Sequence Number? Historically, each TLP carried an explicit sequence number, which, while con... » read more

Smart Handling Of Reset Domain Crossings To Non-Resettable Flip-Flops
By Siemens EDA - 30 Oct, 2025 - Comments: 0

The importance of reset domain crossing (RDC) verification in ensuring robust and reliable SoC operation cannot be overstated. Verification tools for RDCs are essential in identifying potential metastability issues and ensuring that signal transitions across reset domains are properly handled. This paper presents a novel approach to tackling the challenges of RDC verification involving non-rese... » read more

Advances In Formal Verification Technology
By Brian Bailey - 30 Oct, 2025 - Comments: 0

Experts at the table: Semiconductor Engineering sat down to discuss advances in formal verification tools and methodologies with Ashish Darbari, CEO for Axiomise; Jin Zhang, product management group director for the Verification Group at Cadence; Sean Safarpour, executive director for R&D at Synopsys; and Jeremy Levitt, principal engineer for Digital Verification Technology at Siemens EDA.... » read more

Performance Of A Memory System With FeRAM vs. DRAM (Georgia Tech, Imec, NTUA)
By Technical Paper Link - 29 Oct, 2025 - Comments: 0

A new technical paper titled "Benchmarking of FERAM-Based Memory System by Optimizing Ferroelectric Device Model" was published by researchers at Georgia Tech, imec and National Technical University of Athens. Abstract "We present a framework for design technology co-optimization (DTCO) of the main memory system with one transistor-one capacitor (1T1C) ferroelectric random access memory (FE... » read more

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