category: Best Of Both: LP & HP

category: IoT, Security & Automotive

The Seven Pillars Of IC Package Physical Design
By Keith Felton - 15 Feb, 2024 - Comments: 0

Today’s heterogeneously integrated semiconductor packages represent a breakthrough technology that enables dramatic increases in bandwidth and performance with reduced power and cost compared to what can be currently achieved in traditional monolithic SoC designs. Figure 1. A heterogeneously integrated device with 47 chiplets. (Image Source: Intel) The evolving landscape of packagin... » read more

AI-Driven Macro Placement Boosts PPA
By Janet Attar - 11 Jan, 2024 - Comments: 0

In the era of EDA 4.0, artificial intelligence (AI) and machine learning (ML) are transforming what electronic design automation tools are capable of. For many of the challenges of physical IC design, AI can provide significant benefits to both the turnaround time and the quality of the design, as measured by performance, power, and area (PPA) metrics. One implementation step due for improve... » read more

RTL Optimization Best Practices Help To Achieve Power Goals And Identify Reliability Issues Earlier
By Qazi Faheem Ahmed - 09 Nov, 2023 - Comments: 0

Designers face enormous challenges for low-power designs. Whether it is IoT at the edge, AI in the datacenter, robotics or ADAS, the demand for increased functionality and higher performance in SoCs is rapidly stretching power budgets to their breaking point. Power must be considered at every stage of chip design. Waiting to address power until late in the design cycle – post-netlist or durin... » read more

Do You Really Understand The Importance Of Parasitic Extraction In Chip Designs?
By Karen Chow - 12 Oct, 2023 - Comments: 0

By Susanne Lachenmann and Petya Aleksandrova, Infineon Technologies, and Karen Chow, Siemens EDA One of the biggest challenges integrated circuit (IC) designers face in today’s complex designs is effectively managing the effects of parasitic elements such as resistance, capacitance, and inductance. Parasitic elements can significantly impact chip performance of a chip, making it critical f... » read more

No Hot Products
By Mike Donnelly - 14 Sep, 2023 - Comments: 0

While marketers strive to launch the next “hot” product, engineers struggle to prevent literally hot products! A recent breakthrough in thermal modeling comes just in time as electronic component manufacturers and their OEM customers increasingly battle thermal design issues. Analog electronic component manufacturers have traditionally provided models in SPICE format so customers can sim... » read more

Fast, Accurate, Automated Via Insertion During Design Implementation Requires Foundry Rule Compliance
By Jimmy Tien - 10 Aug, 2023 - Comments: 0

As the scaling of silicon technology proceeds, via resistance is becoming a dominant factor in integrated circuit (IC) yield, performance, and reliability. At advanced nodes, interconnects and via dimensions decrease, while the number of metallization layers increases. To moderate the impact of via resistance on yield and reliability and reduce electromigration (EM) and voltage drop (IR) effect... » read more

A New Approach To Design-Stage Layout Optimization Can Speed Time To Tapeout While Improving Power Management
By Jeff Wilson - 20 Jul, 2023 - Comments: 0

The right tool for the job makes all the difference. Ever try hammering a nail in with a rock? How many nails did you ruin before you gave up? Or try to tighten a crucial bolt by hand? It takes forever, and you just can’t tighten it enough, so everything’s still kind of wobbly? Yeah, that’s kind of what it’s like trying to use an electronic design automation (EDA) tool to do a job it’... » read more

How To Answer Five Common Questions About Power Module Current Density
By Wilfried Wessel - 08 Jun, 2023 - Comments: 0

Power module current density is an important factor in determining the efficiency and performance of power modules. This article answers five common questions about power module current density so you can make informed decisions when designing a power module for your application. 1. How many wire bonds are required? Generally, a higher current density requires an increased number of w... » read more

Unblocking The Full Potential Of PCIe Gen6 With Shared Flow Control
By Vidushi Goel - 13 Apr, 2023 - Comments: 0

As technology advances at a rapid pace, PCI Express (or PCIe) has grown tremendously, allowing data transfer up to 64 GT/s in Gen6. This technology is widely used in data centers, artificial intelligence and machine learning computing, high-performance computing accelerators, and high-speed applications—including high-end SSDs, automotive, IoT, and mil-aero. To fully utilize this high-spee... » read more

Low-Power IC Design Without Compromise
By Janet Attar - 09 Mar, 2023 - Comments: 0

In the process of creating ICs, the digital implementation stage is focused on meeting the performance, power, and area (PPA) targets defined for the design. Traditionally, when talking about PPA metrics, “performance” has been the primary focus, with power and area recovered where possible, after meeting timing. But as designs have moved to smaller, more advanced process nodes, and as s... » read more

← Older posts Newer posts →

  • Sponsors

About

Navigation

Connect With Us

Copyright ©2013-2025 SMG   |  Terms of Service  |  Privacy Policy