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What’s In A Name(space)? Optimizing SSD Controller Performance And Verification
By Himani Kaushik - 12 May, 2022 - Comments: 0

Solid state drives (SSDs) have come to the forefront as a promising solution for today and tomorrow’s immense data transfer and storage demands. And SSDs themselves are constantly evolving with upgrades of their critical components to provide higher access speeds. One such component for the NVMe specification is created by the division of non-volatile memory (NVM) into what are commonly known... » read more

Reliable DRC Voltage Text Annotation Means Faster And More Accurate DRC Verification
By Abdellah Bakhali - 14 Apr, 2022 - Comments: 0

As the potential for complex interactions between voltage domains grows significantly with the increase in design density at each new process node, the complexity of spacing checks in design rule checking (DRC) also increases. To minimize these types of risk, many simple spacing checks have evolved to become voltage-aware DRC (VA-DRC) checks that incorporate voltage values to determine the requ... » read more

Shifting The Design Paradigm To Improve Verification Efficiency
By Harry Foster - 10 Mar, 2022 - Comments: 0

We are in the midst of a verification crisis manifested by a growing gap between verification efficiency and effectiveness. This crisis cannot be solved through improvements in verification methodologies and techniques alone. Indeed, it requires a philosophical change in the way we approach design, with an emphasis on bug prevention. We refer to this fundamental change as design using intent-fo... » read more

Context-Aware SPICE Simulation Improves The Fidelity Of ESD Analysis
By Neel Natekar - 10 Feb, 2022 - Comments: 0

Electrostatic discharge (ESD) is a major reliability concern for integrated circuit (IC) designs. ESD verification is proving to be a significant challenge at advanced nodes, due to growing IC design complexity and transistor counts. Traditional ESD verification approaches using parasitic extraction followed by SPICE simulation are deficient in providing simulation results in a practical runtim... » read more

Bug Hunt! Spiraling In On Formal Coverage Closure
By Mark Eslinger - 13 Jan, 2022 - Comments: 0

By Mark Eslinger and Jin Hou Many companies have used formal verification to verify complex SoCs and safety-critical designs. Using formal verification to confirm design functionalities and to uncover functional bugs is emerging as an efficient verification approach. Although formal verification will not handle the complexity of a design at the SoC level, it is an efficient tool to verify th... » read more

Shifting Left In P&R With In-Design Signoff Fill For Faster And More Accurate Tapeouts
By Srinivas Velivala - 09 Dec, 2021 - Comments: 0

Place and route (P&R) engineers are always on the lookout for ways to optimize their design flows to ensure designs meet their design power, performance, and area (PPA) goals while also hitting tapeout deadlines. The introduction of the Calibre RealTime Digital interface made Calibre nmDRC and Calibre nmDRC Recon design rule checking (DRC) verification available during the P&R process t... » read more

Two Methods For Debugging SW Workloads On Arm-Based SoCs
By Andy Meier - 11 Nov, 2021 - Comments: 0

By Andy Meier and Tomasz Piekarz In a typical system-on-a-chip (SoC) development project, chip architects will make a given SoC's initial specification available to design teams years in advance of the silicon. As requirements change, they will modify both the hardware and software specifications. Typically, a large portion of the software development occurs much later in the development pro... » read more

Bringing Scalable Power Integrity Analysis To Analog IC Designs
By Joe Davis - 14 Oct, 2021 - Comments: 0

Power integrity is a broad term in integrated circuit (IC) design and verification. However, when IC engineers are working through design signoff, power integrity analysis focuses on three specific aspects of a design: Power: Verify the chip design as implemented provides the total predicted power under different operating modes. Performance: Find and eliminate performance issues affect... » read more

The Shortest Path Deception
By Derong Yan - 09 Sep, 2021 - Comments: 1

When manufacturing, assembling, and using integrated circuit (IC) chips, the electrostatic discharge (ESD) caused by accumulated static can damage the IC circuitry if the circuit is not properly protected [1]. To prevent such damage, ESD protection devices are designed into the circuitry such that they will create a low impedance path that limits the peak voltage and current by diverting excess... » read more

Now You Can Automate Latch-Up Verification For 2.5/3D Technologies
By Dina Medhat - 12 Aug, 2021 - Comments: 0

Latch-up is modeled as a short circuit (low-impedance path) that can occur in an integrated circuit (IC). It may lead to destruction due to over-current resulting from interactions between parasitic devices (PNP and NPN). To protect against latch-up conditions, there are two key types of latch-up design rules—fundamental and advanced [1,2]. Fundamental rules are the local latch-up design r... » read more

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