category: Blogs – LPHP

category: IoT, Security & Automotive

What A Difference A Decade Makes
By Tiffany Sparks - 22 Sep, 2011 - Comments: 0

By Tiffany Sparks Lately, I find myself in a reflective mood, pondering what’s changed over the past 10 years. Of course, with the 10th anniversary of 9/11 earlier this month, there’s been intense focus on what the world was like 10 years ago and what has changed since that fateful day: the thousands of lives lost, first on 9/11, then the lives lost in Afghanistan and Iraq; the geo-poli... » read more

Picking The Right Models
By Various Writers - 08 Sep, 2011 - Comments: 0

By Ji Zheng As the focus on “efficient computing” increases and ICs are fabricated using process technologies that are more sensitive to voltage fluctuations, accurate modeling and prediction of chip-level, package-level and system-level behavior becomes a necessary design step. The use of chip macro models enables 3D-IC and IC-package-PCB co-analysis for power integrity, signal integrity,... » read more

Hierarchical LP Design 3
By Luke Lang - 08 Sep, 2011 - Comments: 0

By Luke Lang Last month, I wrote in favor of top-down approach to coding the power intent. This month, let’s take a look at the bottom-up approach. With the top-down approach, we code the full-chip power intent without having to worry about all the nets that cross power domain boundaries. Then we issue a few commands, and a tool writes out the block-level CPF. Pretty simple and straightfo... » read more

Interconnect Power II
By Barry Pangrle - 08 Sep, 2011 - Comments: 0

Barry Pangrle After submitting last month’s blog, I read a very interesting article by Deepak Sekar analyzing Intel’s 22 nm FinFET technology versus a hypothetical planar 22nm CMOS technology. Beyond the advantages of being able to use a 140 mV reduction in the supply voltage for the trigate technology, Deepak did a breakdown analysis for the predicted power across a representative micropr... » read more

Powerbenches
By Bhanu Kapoor - 08 Sep, 2011 - Comments: 0

By Bhanu Kapoor Today, in the era of IPs and SoCs, verification consumes up to 70% of the design effort. Most of the rest of the design effort is focused on iterations related to meeting the performance goals. We also hear that power has become the No. 1 design criteria for several categories of semiconductor devices, but we still lack well-defined, power-oriented methodologies and tools that ... » read more

Describing Power Intent
By Ann Mutschler - 08 Sep, 2011 - Comments: 0

Please don’t flame me. I am not aiming this at any one group in particular, but I am always struck at the slowness at which standards efforts move, especially when design teams are the ones really feeling the pain. Case in point: Savita Banerjee, SoC test and verification manager at LSI, told me recently that one of the most important challenges to be solved is a standard way to describe p... » read more

Are Test Engineers More Highly Evolved?
By Kiran Vittal - 25 Aug, 2011 - Comments: 0

In a December 2010 blog, my colleague Ron Craig wrote that 94% of respondents to a survey said that timing constraints were a problem. Well, no surprise there. But 70+% said they planned to simply “try harder” during their next project to avoid these problems. Did they really think that was a viable solution? That blog featured a good illustration of the problem. It gave me a good laugh.... » read more

New Stacking Issues
By Norman Chang - 11 Aug, 2011 - Comments: 0

Reduced form factors, higher performance, and the demand for lower power necessitate the need for 3D-IC/silicon interposer designs with through-silicon vias (TSVs). That also creates major design challenges in three areas. The verification of power, signal, and reliability integrity—particularly with multi-stacked die on silicon interposer with TSVs—presents issues that can only be overcome... » read more

Hierarchical LP Design 2
By Luke Lang - 11 Aug, 2011 - Comments: 0

By Luke Lang Last month, I discussed two key features of the Common Power Format (CPF) that support hierarchical design methodology: boundary port and macro model. These are commands that need to be written to describe the power intent and drive the tools. Without these commands, it is extremely difficult to do hierarchical design. But with these commands, hierarchical power intent files are n... » read more

Interconnect Power
By Barry Pangrle - 11 Aug, 2011 - Comments: 0

By Barry Pangrle Applied Materials announced its latest version of nano-porous low-k dielectric technology called Black Diamond 3 last month at Semicon West. What really caught my ear though was the marketing claim that 1/3 of total chip power consumption (really energy) is in the interconnect. I thought about this a bit, and certainly for some designs this seemed to easily be quite po... » read more

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