An Introduction To Virtual Semiconductor Process Evaluation

By Jeonghoon (James) Kim - 21 Jan, 2021 - Comments: 0

Process engineers develop ideal solutions to engineering problems using a logical theoretical framework combined with logical engineering steps. Unfortunately, many process engineering problems cannot be solved with a brute force, step by step approach to understand every cause-and-effect relationship. There are simply too many process recipe variables that can be modified to make a brute-force... » read more

Process Window Optimization Of DRAM By Virtual Fabrication

By Daebin Yim - 21 Dec, 2020 - Comments: 0

New integration and patterning schemes used in 3D memory and logic devices have created manufacturing and yield challenges. Industrial focus has shifted from the scaling of predictable unit processes in 2D structures to the more challenging full integration of complex 3D structures. Conventional 2D layout DRC, offline wafer metrology, and offline electrical measurements are no longer sufficient... » read more

Accelerating Dry Etch Processes During Feature Dependent Etch

By Timothy Yang - 23 Nov, 2020 - Comments: 0

In dry etching, the trajectory of accelerated ions is non-uniform and non-vertical, due to collisions with gas molecules and other random thermal effects (figure 1). This has an impact on etch results, since the etch rate at any point on the wafer will vary depending on the solid angle visible to the bulk chamber and the ion flux for that angular range. These non-uniform and feature dependent e... » read more

Micro Loading And Its Impact On Device Performance

By Qingpeng Wang - 02 Nov, 2020 - Comments: 0

In a DRAM structure, the charging and discharging process of capacitor-based memory cells is directly controlled by the transistor [1]. With transistor sizes approaching the lower limits of physical achievability, manufacturing variability and micro loading effects are becoming increasingly critical DRAM performance (and yield) limiters. The transistor’s AA (active area) dimension and profile... » read more

Building Predictive And Accurate 3D Process Models

By Pradeep Nanja - 21 Sep, 2020 - Comments: 0

Process engineers and integrators can use virtual process modeling to test alternative process schemes and architectures without relying on wafer-based testing. One important aspect of building an accurate process model is to ensure that the model is calibrated. Having a calibrated model is important, since it provides assurance to the process integrators and engineers that the model will refle... » read more

Understanding Advanced Packaging Technologies And Their Impact On The Next Generation Of Electronics

By Sandy Wen - 28 Aug, 2020 - Comments: 2

Chip packaging has expanded from its conventional definition of providing protection and I/O for a discrete chip to encompassing a growing number of schemes for interconnecting multiple types of chips. Advanced packaging has become integral to embedding increased functionality into a variety of electronics, such as cellular phones and self-driving vehicles, by supporting high device density in ... » read more

Semiconductor Memory Evolution And Current Challenges

By Michael Hargrove - 16 Jul, 2020 - Comments: 0

The very first all-electronic memory was the Williams-Kilburn tube, developed in 1947 at Manchester University. It used a cathode ray tube to store bits as dots on the screen’s surface. The evolution of computer memory since that time has included numerous magnetic memory systems, such as magnetic drum memory, magnetic core memory, magnetic tape drive, and magnetic bubble memory. Since the 19... » read more

Introducing Nanosheets Into Complementary-Field Effect Transistors (CFETs)

By Benjamin Vincent - 01 Jun, 2020 - Comments: 0

In our November 2019 blog [1], we discussed using virtual fabrication (SEMulator3D) to benchmark different process integration options for Complementary-FET (CFET) fabrication. CFET is a CMOS architecture that was proposed by imec in 2018 [2]. This architecture contains p- and n-MOSFET structures built on top of each other, instead of having them located side-by-side. In our previous blog, we r... » read more

Identifying And Preventing Process Failures At 7nm

By Qingpeng Wang - 20 Apr, 2020 - Comments: 0

Device yield is highly dependent upon proper process targeting and variation control of fabrication steps, particularly at advanced nodes with smaller feature sizes. Traditionally, cross-correlation and analysis of thousands of test data points have been required to identify and prevent process failures. This is very costly in terms of both time and money. Fortunately, semiconductor virtual fab... » read more

The Impact Of EUV Resist Thickness On Via Patterning Uniformity

By Benjamin Vincent - 30 Mar, 2020 - Comments: 0

Via patterning at advanced nodes requires extremely low critical dimension (CD) values, typically below 30nm. Controlling these dimensions is a serious challenge, since there are many inherent sources of variation during lithography and etch processing. Coventor personnel, in conjunction with our colleagues from ASML and imec, recently looked at the impact of Extreme Ultraviolet lithography (EU... » read more

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category: Perfecting The Process

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An Introduction To Virtual Semiconductor Process Evaluation

Process Window Optimization Of DRAM By Virtual Fabrication

Accelerating Dry Etch Processes During Feature Dependent Etch

Micro Loading And Its Impact On Device Performance

Building Predictive And Accurate 3D Process Models

Understanding Advanced Packaging Technologies And Their Impact On The Next Generation Of Electronics

Semiconductor Memory Evolution And Current Challenges

Introducing Nanosheets Into Complementary-Field Effect Transistors (CFETs)

Identifying And Preventing Process Failures At 7nm

The Impact Of EUV Resist Thickness On Via Patterning Uniformity

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