category: Low Power-High Performance

category: IoT, Security & Automotive

Attaching Fibers To Photonic Chips
By Paul McLellan - 10 Dec, 2020 - Comments: 0

Recently, Cadence held its fifth photonics summit, CadenceCONNECT: Photonics Contribution to High-Performance Computing. You can read my earlier posts: Photonic Integration—From Switching to Computing How to Design Photonics If You Don't Have a PhD: iPronics and Ayar Labs The third day was all about how to connect the incoming and outgoing fibers to the photonics chips. I will cov... » read more

Standard Benchmarks For AI Innovation
By Dylan Zika - 10 Dec, 2020 - Comments: 0

There is no standard measurement for machine learning performance today, meaning there is no single answer for how companies build a processor for ML across all use cases while balancing compute and memory constraints. For the longest time, every group would pick a definition and test to suit their own needs. This lack of common understanding of performance hinders customers' buying decis... » read more

Pushing The Envelope With HBM2E Memory
By Joseph Rodriguez - 10 Dec, 2020 - Comments: 0

In September, Rambus announced the achievement of reaching 4 gigabits per second (Gbps) operation with our HBM2E memory interface. This milestone was demonstrated in silicon and required mastering substantial signal integrity and power integrity (SI/PI) challenges. The 4 Gbps mark represents a 20% rise from the previous maximum data rate of 3.2 Gbps for HBM2E. To date, the industry’s faste... » read more

Waking And Sleeping Create Current Transients
By Bryon Moyer - 10 Dec, 2020 - Comments: 0

Silicon power-saving techniques are helping to reduce the power required by data centers and other high-intensity computing environments, but they’ve also added a significant challenge for design teams. As islands on high-powered chips go to sleep and wake up, the current requirements change quickly. This happens in a few microseconds, at most. The rapid change of loading creates a challen... » read more

Simulating The Hyperloop
By Susan Coleman - 10 Dec, 2020 - Comments: 0

When SpaceX held the first Hyperloop Design Weekend Competition in Texas in January 2016, a team of five students from the Universitat Politècnica de València (UPV) in Spain, calling themselves Hyperloop UPV, won awards for Best Overall Concept Design and Best Propulsion System. The overall concept was to use magnetic levitation to give their Hyperloop vehicle a frictionless ride through t... » read more

An Integrated Approach To Power Domain And Clock Domain Crossing Verification
By Mentor, a Siemens Business - 09 Dec, 2020 - Comments: 0

Reducing power consumption is essential for both mobile and data center applications. The challenge is to lower power while minimally impacting performance. The solution has been to partition designs into multiple power domains which allow selectively reducing voltage levels or powering off partitions. Traditional low power verification validates only the functional correctness of power control... » read more

Towards Self-Driving Cars: MIPI D-PHY Enabling Advanced Automotive Applications
By Mixel - 09 Dec, 2020 - Comments: 0

Because both viewing and sensing ADAS applications must handle imaging, sensing, high-speed serial communication, and downstream processing functions, Camera Video Processors (CVPs) are always located at the heart of these systems. As more cameras and sensors are added to the system to aid in increasingly complicated tasks, more integrated CVP solutions are required. Ideally, these CVPs should ... » read more

HPC Appliance Boosts Simulation Performance
By Ansys - 09 Dec, 2020 - Comments: 0

High-performance computing (HPC) resources can provide a substantial boost to simulation, but an HPC cluster can be complex and difficult to manage. By deploying a managed HPC cluster for ARA, the client was able to eliminate internal maintenance and support overhead, while improving productivity and reliability for their Ansys workloads. Click here to read more. » read more

How To Speed Up Large-Scale EM Simulation Of ICs Without Compromising Accuracy
By Cadence - 09 Dec, 2020 - Comments: 0

With growing on-chip radio frequency (RF) content, electromagnetic (EM) simulation of the passives is critical for a variety of reasons — from selecting the right RF design candidates to detecting parasitic coupling that directly impacts performance. Being on-chip, accurate EM analysis requires a tie into the process technology in the form of process design kits (PDKs) as well as a foundry-ce... » read more

Powering The Edge: Driving Optimal Performance With Ethos-N77 Processor
By Arm - 09 Dec, 2020 - Comments: 0

Repurposing a CPU, GPU, or DSP is an easy way to add ML capabilities to an edge device. However, where responsiveness or power efficiency is critical, a dedicated Neural Processing Unit (NPU) may be the best solution. In this paper, we describe how the Arm Ethos-N77 NPU delivers optimal performance. Click here to immediately download the paper. » read more

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