Week In Review: Manufacturing, Test


Chipmakers Intel posted its quarterly results. But the big question is whether the chip giant will outsource more of its production to the foundries. As reported, Intel has fallen behind TSMC and Samsung in process technology. And Intel may need to outsource some of its chip production to stay ahead. All of this rests on Pat Gelsinger, the new CEO at Intel. Gelsinger will be taking over for... » read more

Fearless Chip Forecasts For 2021


It’s been a roller coaster ride in the semiconductor industry. In early 2020, the semiconductor business looked bright, but then the Covid-19 pandemic struck, causing a sudden downturn. By mid-2020, though, the market bounced back, as the stay-at-home economy drove demand for computers, tablets and TVs. The chip market ended on a high note in 2020, but the question is, what’s in store fo... » read more

A Look Inside ADAS Modules


You glance down at your phone while rolling in slow-moving traffic. Against your better judgment, you proceed to read your latest email, oblivious to the fact that the car in front of you has braked. In the nick of time, your car starts beeping and flashing. You look up and slam the brakes. Whew! That was close. If this has happened to you, don't forget to thank the radar and camera modules in ... » read more

The Chip Industry’s Next-Gen Roadmap


Todd Younkin, the new president and chief executive of the Semiconductor Research Corp. (SRC), sat down with Semiconductor Engineering to talk about engineering careers, R&D trends and what’s ahead for chip technologies over the next decade. What follows are excerpts of that conversation. SE: As a U.S.-based chip consortium, what is SRC's charter? Younkin: The Semiconductor Research... » read more

An Introduction To Virtual Semiconductor Process Evaluation


Process engineers develop ideal solutions to engineering problems using a logical theoretical framework combined with logical engineering steps. Unfortunately, many process engineering problems cannot be solved with a brute force, step by step approach to understand every cause-and-effect relationship. There are simply too many process recipe variables that can be modified to make a brute-force... » read more

Eyes On Zero Defects: Defect Detection And Characterization Metrology


By Darin Collins and Jessica Albright Metrology is the science of measuring, characterizing, and analyzing materials. Within metrology, there are several technologies used to detect material defects on a very small scale – precision on the scale of parts per trillion or less is necessary in the pursuit of zero defects. We broadly define our characterization approach into three main categor... » read more

48V Applications Drive Power IC Package Options


The manufacturing process and die get most of the attention, but the packaging plays an important part in enabling and limiting performance, manufacturability, particularly when it comes to reliability of power devices. Given the wide range of underlying semiconductor power-device technologies — “basic” silicon, wide-bandgap silicon carbide (SiC) and gallium nitride (GaN), power levels... » read more

Mobility And 5G Drive Adoption Of New Materials For Power Devices


Electric mobility, renewable energy, and other technology innovations like IoT, 5G, smart manufacturing, and robotics all require reliability, efficiency, and compact power systems, fueling the adoption of silicon carbide (SiC) and gallium nitride (GaN) to support lower voltages in significantly smaller devices. But chip designers must overcome the technological and economical challenges of int... » read more

Stronger, Better Bonding In Advanced Packaging


System-in-package integrators are moving toward copper-to-copper direct bonding between die as the bond pitch goes down, making the solder used to connect devices in a heterogenous package less practical. In thermocompression bonding, protruding copper bumps bond to pads on the underlying substrate. In hybrid bonding, copper pads are inlaid in a dielectric, reducing the risk of oxidation. ... » read more

A Triple-Deck CFET Structure With An Integrated SRAM Cell For The 2nm Technology Node And Beyond


A novel triple-deck CFET structure is proposed for the first time as a candidate for area scaling. The proposed triple-deck CFET aggressively stacks a pass gate over an inverter to form a half SRAM bit cell. The integration flow and full metal connectivity have been carefully designed for functionality and array assembly. Most of the pitch used in the process is around 40nm, which is patternabl... » read more

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