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48V Applications Drive Power IC Package Options

As newer power-semiconductor processes become mainstream, new packaging approaches are required for thermal and parasitic issues .


The manufacturing process and die get most of the attention, but the packaging plays an important part in enabling and limiting performance, manufacturability, particularly when it comes to reliability of power devices.

Given the wide range of underlying semiconductor power-device technologies — “basic” silicon, wide-bandgap silicon carbide (SiC) and gallium nitride (GaN), power levels, and applications — it’s not surprising that the universe of power-device packages is both wide and deep. There also are different package types and internal configurations optimized for specific markets and their priorities. Even with that selection, the higher figure of merit (FOM) for wide-bandgap devices, with their increased efficiency, higher operating temperature and switching frequencies, and potentially higher output power, is placing new demands on packaging. SiC, for example, is in the 175⁰C range. At the same time, there are pressures for higher levels of functional integration, putting multiple power devices — and even their drivers — within a package.

Because wide-bandgap devices are more efficient and thus dissipate less heat, it might seem that the never-ending thermal challenge of keeping the die below its maximum junction temperature would be lessened. That tends not to be the case, however.

“Packaging is easier if the die is efficient,” said Shaun Bowers, vice president of package development and technology integration at Amkor. The problem is that expectations of users of these power devices grow faster than the improvements in the devices themselves. As a result, what was once considered a performance ceiling becomes the floor. Thus, along with lower on-resistance (RDS(ON)), the new-design imperatives include reduction in parasitics. This is primarily inductance Lds, but it also includes capacitance Ciss for higher switching speeds, reduced interconnect resistance, integration with passive components and even control logic. And all of this happens with a smaller overall package size, both in terms of footprint and thickness.

Thermal considerations are always present, of course. This is analogous to the situation faced by designers of low-level signal-processing systems, who recognize that external and internal noise define their ultimate design limit. Similarly, power engineers know that thermal issues head the list of design constraints, and they are always lurking in the background.

“Getting rid of the heat is the big challenge,” said Sam Sadri, senior process engineer at Quik-Pak. “The most common approach is to attach a chip to a copper heat sink, which is cheap and a good heat conductor. But you also can use aluminum nitride, which has a coefficient of thermal expansion that is very close to silicon. That’s particularly important in packaging.”

The overwhelming need to provide power components in surface-mount device packages rather than the older through-hole design with large leads is changing the heat-flow path strategy. Basic surface-mount package styles include the power quad flat no-lead package (PQFN), exposed double-decawatt package (eD2PAK), TO-leadless (TOLL) package, and loss-free package (LFPAK). On the thermal side, dual-side cooling is a big deal for SiC devices, said Amkor’s Bowers.

Fig. 1: Six of the many standard package types used for power devices. The external photos don’t reveal their internal structures or arrangements, but they are complex and sophisticated. Source: Amkor

Packaging innovations rely on three primary advances:

    • The electrical conductivity from device source to drain must be increased to reduce losses and subsequent heat generation;
    • As many thermal or electrical interfaces as possible should be eliminated, because each represents a barrier as well as potential point of failure due to thermal cycling, mismatch between coefficients of thermal expansion (CTE), and manufacturing issues, and
    • The thermal performance of the packaging material itself must be improved.

Transition from 12V to 48V drives new packaging
With power there is one unavoidable fact as defined by basic principles of physics and electricity — when delivering power (the product of voltage and current) from a source to a load, the resistive losses and thus heat dissipation increase with the square of the current (I2R). As has been known from the earliest days of electricity, the use of higher operating voltages allows for lowered currents and is the best and often the only way to sufficiently cut losses, heat, and inefficiency to an acceptable value at a given power level.

Therefore, as power demands inexorably increase, the long-established 12-volt standard as the intermediate bus voltage for data centers is falling short in its ability to deliver the needed power at low-enough loss and with acceptable efficiency. Instead, power rails are shifting to 48 volts.

The same voltage-rail transition is occurring in automotive designs for vehicles with internal combustion engines, as well as “mild” hybrid electric vehicles, where a 48-volt bus is needed to support the many higher-power loads, including the starter, electric-steering assist, and many other motors.

This transition from 12V to 48V as the primary rail in data centers, as well as a second rail in automotive power subsystems —there is also the emergence of 57V for 5G base stations — is driving two trends in package development. These dual paths are due to the difference in the primary performance objectives for each.

Data-center servers require a fast transient ramp-up response to efficiently support the rapid transitions in processor-power demands. This has led to the use of point-of load architectures operating at switching frequencies of 1MHz and above, but the parasitic impedance of power-device packages limits transient performance at that frequency.

To overcome this, for example, Amkor is investigating a new approach called the PowerCSP package (PCSP), which reinvents chip-scale packaging for power-focused applications. It meets the three improved-package objectives of improved drain-source conductivity, fewer electrical and thermal interfaces, and higher thermal conductivity of materials, while also reducing the overall device size.

Fig 2: PowerCSP technology offers many user options, including attached heat spreader, heat spreader with side wall for EMC shielding, materials with high thermal and electrical conductivity, which may be soldered or sintered, and wettable flank. Source: Amkor

This leadframe-based chip-scale packaging supports double-side cooling where the top/leadframe side can be connected to the heat sink, while the bottom side of the package can be mounted to the PC board using thermal vias and copper layers. The PCSP eliminates wire bonds and/or copper clips, which results in low parasitic resistances and stray inductances for reduced conduction losses and switching losses, respectively.

Fig 3: Simulated comparison of RDS, LDS and Ciss for Amkor’s PowerCSP (PCSP) design versus different versions of eD2PAK, TOLL and LFPAK packages. Source: Amkor

In contrast to the needs of data centers, the performance priority for automotive 48-volt power is not microsecond-fast transient response. Instead, it needs to deliver several hundred amps to the starter/generator assembly in the classic three-phase, half-bridge arrangement with high- and low-side power devices. This is relatively intermittent demand, even with the stop-start gas-saving design mode of many new vehicles, but the high current levels along with power levels in the tens of kilowatts often requiring use of multiple MOSFETs.

To facilitate this arrangement, package vendors are looking to new structures which exploit the opportunity to house multiple MOSFETs and even their support passives in a single package. ASE has its Advanced Embedded Active System Integration (a-EASI ) power-package platform, which fits single and half-bridge topologies, with low bulk-silicon resistivity for low-impedance vertical current flow and thus low RDS(ON). ASE also has developed a set of heat-spreader and clip-based QFN approaches of this application, with clearly differentiated performance characteristics

Fig. 4: The Advanced Embedded Active System Integration (aEASI) approach supports three distinct structures (P1, P2, P3) with differing attributes. Source: ASE

Fig. 5: The compared resistance and efficiency graphs of the aEASI P1, P2, and P3 structures, as well as the PQFN device with Cu clip. Source: ASE

ASE also is addressing the challenge of co-packaging inductors, a necessary but hard-to-integrate passive component in switching power circuits, with solutions such as package-on-package, which also meets the challenge of thick mold cap requirements for molded integration.

Fig. 6: Multiple views of the Package-on-Package (POP) arrangement with a co-mounted inductor. Source: ASE

Further, as with all technology advances, there is always an ongoing, back-and-forth resonating reinforcement between developments initially targeting one issue and application in other areas. Mark Gerber, senior director of technical marketing and engineering at ASE, pointed out that thermal mold compounds and advanced thermal interface materials (TIMs), which reduce thermal impedance can be leveraged by non-power devices focused on digital applications. Other possibilities under investigation include using carbon nanotubes, which are now widely available and being utilized in academic projects across many disciplines from sensors to thermal applications.

Isolated devices add to the challenge
A widely used element of the total thermal path from the dies and then out of and away from the package is to embed an electrically and thermally conductive pad under the package. However, this is not viable in common circuit topologies such as bridge arrangements, where some of the power devices, as well as their gate drivers, must have galvanic (ohmic) isolation from the system ground. [Note: The term “ground” is often a misnomer. A better term is the system common.]

Therefore, vendors are developing packages that support higher thermal conductivity while using film and metallized pedestals to maintain needed electrical insulation from the board. The insulation thickness and other parameters must be sufficient to withstand the potential difference in the path between isolated component and common, to meet both basic electrical requirements and regulatory mandates. Further, as power-component voltages increase, the minimum creepage and clearance dimensions also increase, further complicating package geometry. If an underside thermal pad is electrically unacceptable, there are packages with a heat sink pad on the top side for cooling by passive or forced airflow. However, this may not be as desirable from a system perspective as using a bottom-side pad, which leverages circuit-board copper as a heat spreader.

It’s not just autos and data centers that are seeing technical and regulatory changes. Even consumer products and their components are affected by new regulations. Long-established independent safety standards for information-technology equipment (IEC 60950-1) and audio-visual equipment (IEC 60065) were merged, updated, and withdrawn as of December 2020, and replaced by the single ANSI/IEC 62368-1 (“Audio/video, information and communication technology equipment – safety requirements”) standard in North America and the EU. The new standard introduces a different hazard-based philosophy to product testing than its predecessors, and high-voltage considerations are among the many issues it addresses. Gerber noted that ASE is experienced in high-voltage isolation and can design and manufacture low-temperature co-fired ceramic devices with excellent isolation properties to support high voltage/power requirements.

Up-front modeling, production issues also impact package improvements
It’s one thing to conceptually devise innovations which meet new objectives while striking a balance among the various tradeoffs and constraints. It’s quite another to simulate the performance in detail before prototypes are crafted and tested. ASE’s Gerber, along with Amkor’s Bowers and Sophie Olson, senior manager of package development and technology integration at Amkor, agree that Ansys’ tools are the most widely used for this purpose. But they also note that as packaging systems become more complex – and these tiny packages and die are systems, despite their relatively few and all-static parts – this is also an increasingly difficult challenge.

Olson noted that these tools are used to do basic multi-physics thermal, mechanical, and electrical simulation to determine junction temperature and other key parameters. While they are adequate for the design phase, customers must model the transient performance using their own die. Bowers pointed out that it depends on the customer as well. Some are knowledgeable, and package vendors can learn from them. Others, meanwhile, are better at up-front concepts and design, but don’t know materials or die-attach issues as well, and therefore need help from the package vendor.

Higher power density and thermal issues also have less visible impact. Amkor’s Olson pointed out that silver sintering — the welding together of small particles of metal by applying heat just below the melting point — is often now more suitable for interconnects than soldering, and is also better for meeting RoHS requirements. “Regulations usually work against us, but here it helps,” she said. Olson added that when solder is used, there is “social pressure” from customers – not regulatory-driven – to use recycled tin solder. Because tin can be 100% recycled, Amkor makes use of recycled material when possible.

Advances in the capabilities of semiconductor power devices oscillate between the performance of the bare unpackaged die and commercially available packaging. New package concepts, arrangements, and materials, along with enhanced manufacturing techniques, allow these process advances (such as SiC or GaN) or user needs (the push to 48-V rails) to become system building blocks and architectures.

Power devices have only a few connections between die and board, in contrast to digital ICs with their high lead count. This both simplifies and complicates their paths to successful adoption. Package designers are charged with more than just keeping up with new die and process requirements, as they must also anticipate needs and provide the vehicles enable them to be viable products.

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Rich Blish says:

Very well written and informative article, even to a retired packaging engineering manager.

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