Novel Etch Technologies Utilizing Atomic Layer Process For Advanced Patterning


We demonstrated a high selective and anisotropic plasma etch of Si3N4 and SiC. The demonstrated process consists of a sequence of ion modification and chemical dry removal steps. The Si3N4 etch with H ion modification showed a high selectivity to SiO2 and SiC films. In addition, we have developed selective etch of SiC with N ion modification. On the other hand, in the patterning etch processes,... » read more

Process Variation Analysis of Device Performance Using Virtual Fabrication


A new methodology is demonstrated to assess the impact of fabrication inherent process variability on 14-nm fin field effect transistor (FinFET) device performance. A model of a FinFET device was built using virtual device fabrication and testing. The model was subsequently calibrated on Design of Experiment corner case data that had been collected on a limited number of processed fab wafers. W... » read more

AI And High-NA EUV At 3/2/1nm


Semiconductor Engineering sat down to discuss lithography and photomask issues with Bryan Kasprowicz, director of technology and strategy and a distinguished member of the technical staff at Photronics; Harry Levinson, principal at HJL Lithography; Noriaki Nakayamada, senior technologist at NuFlare; and Aki Fujimura, chief executive of D2S. What follows are excerpts of that conversation. To vie... » read more

New RDL-First PoP Fan-Out Wafer-Level Package Process With Chip-to-Wafer Bonding Technology


Fan-Out Wafer-Level Interposer Package-on Package (PoP) design has many advantages for mobile applications such as low power consumption, short signal path, small form factor, and heterogeneous integration for multifunctions. In addition, it can be applied in various package platforms, including PoP, System-in-Package (SiP), and Chip Scale Package (CSP). These advantages come from advanced inte... » read more

A Production-Worthy Fan-Out Solution — ASE FOCoS Chip Last


The 5th Generation (5G) wireless systems popularity will push the package development into a high performance and heterogeneous integration form. For high I/O density and high performance packages, the promising Fan Out Chip on Substrate (FOCoS) provides a solution to match outsourced semiconductor assembly and testing (OSAT) capability. FOCoS is identified the Fan Out (FO) package, which can f... » read more

Manufacturing Bits: Dec. 15


Ghost imaging quantum microscopes The U.S. Department of Energy’s (DOE) Brookhaven National Laboratory has begun building a quantum-enhanced X-ray microscope based on a technology called ghost imaging. Still in R&D, quantum X-ray microscopes promise to provide higher resolution images with less damage to a sample. Using the National Synchrotron Light Source II (NSLS-II), researcher... » read more

Week In Review: Manufacturing, Test


Government policy--semiconductors Eighteen members of the European Union have launched an initiative to boost the EU’s efforts in processors and semiconductor technologies. The member nations will also work together to bolster leading-edge manufacturing capacity. The EU plans to invest up to $145 billion in the effort. “Europe has all it takes to diversify and reduce critical dependenci... » read more

Manufacturing Bits: Dec. 7


Cybersecurity for manufacturing The University of Texas at San Antonio (UTSA) has launched a center to address cybersecurity issues in the U.S. manufacturing sector. The center, called the Cybersecurity Manufacturing Innovation Institute (CyManII), is a $111 million public-private partnership. As part of the effort, UTSA will enter into a five-year corporative agreement with the U.S. Depart... » read more

Week In Review: Manufacturing, Test


Packaging and EMS ASE is expanding its efforts in the electronic manufacturing services (EMS) business. Universal Scientific Industrial (USI), a subsidiary of ASE, has completed the acquisition of Asteelflash Group through the acquisition of its parent company, Financière. USI provides electronic design and manufacturing services. It also provides system-in-package (SiP) modules. Asteelfla... » read more

Manufacturing Bits: Dec. 1


New phase-change materials The National Institute of Standards and Technology (NIST) has developed an open source machine learning algorithm for use in discovering and developing new materials. NIST’s technology, called CAMEO, has already been used by researchers to discover a new phase-change memory material. CAMEO, which stands for Closed-Loop Autonomous System for Materials Exploration... » read more

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