category: Test, Measurement and Analytics

category: IoT, Security & Automotive

Nip The Defect In The Bud
By Melvin Lee - 12 Apr, 2022 - Comments: 0

As technology nodes shrink, end users are designing systems where each chip element is being targeted for a specific technology and manufacturing node. While designing chip functionality to address specific technology nodes optimizes a chip’s performance regarding that functionality, this performance comes at a cost: additional chips will need to be designed, developed, processed, and assembl... » read more

Finding And Applying Domain Expertise In IC Analytics
By Anne Meixner - 12 Apr, 2022 - Comments: 0

Behind PowerPoint slides depicting the data inputs and outputs of a data analytics platform belies the complexity, effort, and expertise that improve fab yield. With the tsunami of data collected for semiconductor devices, fabs need engineers with domain expertise to effectively manage the data and to correctly learn from the data. Naively analyzing a data set can lead to an uninteresting an... » read more

Automate Memory Test Through A Shared Bus Interface
By Harshitha Kodali - 12 Apr, 2022 - Comments: 0

The use of memory-heavy IP in SoCs for automotive, artificial intelligence (AI), and processor applications is steadily increasing. However, these memory-heavy IP often have only a single access point for testing the memories. A shared bus architecture allows testing and repairing memories within IP cores through a single access point referred to as a shared bus interface. Within this interface... » read more

Case Study — 3D Wire Bond Inspection and Metrology
By CyberOptics - 12 Apr, 2022 - Comments: 0

The growing amount of electronics within modern vehicles has made the inspection process for wire bonds increasingly challenging, as active devices shrink and bonds are arranged in complex ways. CyberOptics addressed the need for an automated solution to replace labor-intensive and imprecise manual inspection methods for wire bonds and loop heights. After consideration of competitive products, ... » read more

Detecting Spatial Blotches In Image Sensor Devices
By Christos Pantelidis - 12 Apr, 2022 - Comments: 0

One of the most common defects in image sensor devices is spatial blotches. The appearance of blotches in image sensors is a regular occurrence and may be generated by internal moving parts or may be moved by air currents within the camera. Composed of two main statistical methods, the first module employs an inferential method, applying a spatial segmentation of the current frame to obtain ... » read more

Extracting Intrinsic Mechanical Properties Of Thin Low-Dielectric Constant Materials With iTF Analysis
By Bruker - 12 Apr, 2022 - Comments: 0

This white paper focuses on the optimization and use of Bruker’s iTF software package for the extraction of intrinsic (substrate independent) mechanical properties, particularly for thin, low-k materials. These considerations are split into two main parts: Measurement procedure (Section II) and iTF execution (Section III). The former outlines important aspects of acquiring proper experimental... » read more

Made in the Cloud!
By Synopsys - 12 Apr, 2022 - Comments: 0

While software developers have been building and delivering software in the cloud for many years now, how much IC hardware is “made in the cloud”? We’re here to help you understand the case for IC hardware development in the cloud and answer the most common questions. Download the paper and learn: Why isn’t everybody doing it? Why cloud? Why now? Can you afford to ignore i... » read more

Silicon Lifecycle Management’s Growing Impact On IC Reliability
By Ed Sperling - 12 Apr, 2022 - Comments: 0

Experts at the Table: Semiconductor Engineering sat down to talk about silicon lifecycle management, how it's expanding and changing, and where the problems are, with Prashant Goteti, principal engineer at Intel; Rob Aitken, R&D fellow at Arm; Zoe Conroy, principal hardware engineer at Cisco; Subhasish Mitra, professor of electrical engineering and computer science at Stanford University; a... » read more

Site-To-Site Variation In Parallel Test
By Ed Seng - 16 Mar, 2022 - Comments: 0

From wafer to system level test, parallel test execution delivers significant benefits, including reduced costs, yet it’s never as simple as that PowerPoint slide you present to management. An engineering effort is required to balance the thermo-electrical challenges that occur as you increase the number of sites to be tested, or the number of slots in a burn-in oven or system level te... » read more

Fundamental Shifts In IC Manufacturing Processes
By Ed Sperling - 14 Mar, 2022 - Comments: 2

High chip value and 3D packaging are changing where and how tests are performed, tightening design-for-reliability and accelerating the shift of tools from lab to fab. Heterogeneous integration and more domain-specific designs are causing a string of disruptions for chip manufacturers, up-ending proven fab processes and methodologies, extending the time it takes to manufacture a chip, and ul... » read more

← Older posts Newer posts →

  • Sponsors

About

Navigation

Connect With Us

Copyright ©2013-2024 SMG   |  Terms of Service  |  Privacy Policy