category: System-Level Design

category: IoT, Security & Automotive

Enabling Innovative Multi-Vendor Chiplet-Based Designs
By Elad Alon - 26 Sep, 2024 - Comments: 0

Chiplets have emerged as a critical implementation paradigm for semiconductor products, primarily because they can deliver cost benefits relative to a non-chiplet-based approach. The first, most well-proven, and obvious benefit of a chiplet-based approach is manufacturing cost. Manufacturing cost benefits are accrued either from the appropriate selection of chiplet die size, or by optimizin... » read more

Using AI To Glue Disparate IC Ecosystem Data
By Ed Sperling and Ann Mutschler - 26 Sep, 2024 - Comments: 0

AI holds the potential to change how companies interact throughout the global semiconductor ecosystem, gluing together different data types and processes that can be shared between companies that in the past had little or no direct connections. Chipmakers always have used abstraction layers to see the bigger picture of how the various components of a chip go together, allowing them to pinpoi... » read more

Managing Performance in Modern SoC Designs
By John Min - 26 Sep, 2024 - Comments: 0

As industries like automotive, consumer electronics, telecommunications and artificial intelligence (AI) push for greater processing power, efficiency and scalability, system-on-chip (SoC) designs have rapidly evolved to meet these demands. With the growing complexity of modern SoCs, designers face the challenge of managing an increasing number of interconnected IP blocks while ensuring seamles... » read more

DDR5 UDIMM Evolution To Clock Buffered DIMMs (CUDIMM)
By Shyam Sharma - 26 Sep, 2024 - Comments: 0

DDR5 is the latest generation of PCDDR memory that is used in a wide range of application like data centers, Laptops and personal computers, autonomous driving systems, servers, cloud computing, and gaming are now increasingly being used for AI applications with advances in memory bandwidth and density to allow DDR5 DIMMs (Dual Inline Memory Modules) to support densities higher then 256 GB per ... » read more

RAG-Enabled AI Stops Hallucinations, Adds Sources
By Karen Heyman - 26 Sep, 2024 - Comments: 0

Many EDA companies have taken the first steps to incorporate generative AI into their tools, and in such tightly controlled environments GenAI appears to have great benefits. But its broader adoption has been delayed by its notorious inaccuracy, giving results that are often out of date, untrue, and unsourced. That's starting to change. GenAI is evolving so rapidly that these kinds of proble... » read more

Signal Integrity Basics
By Siemens EDA - 26 Sep, 2024 - Comments: 0

In this orientation to signal integrity basics, we aim to introduce several important and fundamental concepts of signal integrity for the beginner. Most explanations are provided at a high level without a lot of depth and math, and examples are provided with a focus on comparison rather than detailed numerical results. Of course, background depth, math, and numerical details are very important... » read more

Pressure Builds To Adopt Virtual Prototypes
By Brian Bailey - 26 Sep, 2024 - Comments: 0

Virtual prototypes, often used as a niche tool in the past, are becoming essential for developing complex systems. In fact, systems companies are finding they no longer can function without them. In the semiconductor industry, a virtual prototype is a model for a system at an abstraction level above RTL. But there is no such thing as 'the' virtual prototype. They are constructed for a partic... » read more

Maximizing Coverage Metrics with Formal Unreachability Analysis
By Synopsys - 25 Sep, 2024 - Comments: 0

Coverage lies at the very heart of functional verification. Whether designing a single intellectual property (IP) block or a huge system on chip (SoC), verification teams need to know how well the design has been tested. Functional coverage, code coverage, toggle coverage, assertion coverage, and other metrics are widely used. Improving tests to fill in coverage holes is a key part of the proce... » read more

Impact of Finite Interconnect Impedance Including Spatial and Domain Comparison of PDN Characterization
By Cadence - 25 Sep, 2024 - Comments: 0

Abstract Over the past few decades, a lot of details have been worked out in power distribution network design, simulation and measurement. We have well-established PDN design procedures both in the frequency and time domains, we have simulation tools that can analyze the physical structure from DC to very high frequencies, including spatial variations of the behavior, and we also have fre... » read more

UMI Can Scale the Memory Wall
By Eliyan - 25 Sep, 2024 - Comments: 0

While the improvements in processor performance to enable the incredible compute requirements of applications like Chat-GPT get all the headlines, a not-so-new phenomenon known as the memory wall risks negating those advancements. Indeed, it has been clearly demonstrated that as CPU/GPU performance increases, wait time for memory also increases, preventing full utilization of the processors. ... » read more

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