Eliminating Software Development Bottlenecks For SoCs


System on chip (SoC) devices, by definition, use a combination of hardware and embedded software to provide their specified functionality. Both the design and programming teams face many challenges and have huge tasks. No matter how well they may perform, the full system cannot be verified and validated until the hardware and software are brought together in the bring-up lab. This is usually wa... » read more

Improving Predictability Through Design Solutions Methodologies


“Plans are useless, but planning is indispensable.” – Dwight D. Eisenhower Our first article called for the need to change how we think about verification. In this follow-up, we dive deeper into the tools needed for today’s verification. Project milestones are destined to move. Development estimates are rough and almost always optimistic. Each development stage contains interdepe... » read more

Raising The Bar With The Next Generation Of AI For Chip Design


The semiconductor industry is enjoying renewed growth despite chip shortages plaguing everything from cars to kitchen appliances. But while the chips themselves continue to get faster and smarter, the chip design process itself hasn’t changed that much in 20+ years. It typically takes 2-3 years to design a chip with a large engineering team and tens or hundreds of millions of dollars to get a... » read more

Batch Filters: A Better, Faster Way To Filter Large DRC Results Databases


Reviewing massive DRC results databases (RDBs) can be a time-consuming stage in traditional debug flows, due primarily to the loading, filtering, and display times associated with these large datasets. Finding the most effective approach to filtering results data is important to optimize both results debug time and resource usage. While smaller databases that load quickly in GUI applications ca... » read more

Interop Shift Left: Using Pre-Silicon Simulation for Emerging Standards


The Compute Express Link (CXL) 2.0 specification, released in 2020, accompanies the latest PCI Express (PCIe) 5.0 specification to provide a path to high-bandwidth, cache-coherent, low-latency transport for many high-bandwidth applications such as artificial intelligence, machine learning, and hyperscale applications, with specific use cases in newer memory architectures such as disaggregated a... » read more

Week In Review: Design, Low Power


Tools Imperas Software released updated simulator and reference models that support the latest RISC-V extensions for Bit Manipulation 1.0.0, Cryptographic (Scalar) 1.0.0, and Vector 1.0, plus Privilege Specification 1.12. They are offered both as freely available, open-source reference models for the RISC-V community as well as commercial products. Ansys' multiphysics signoff solutions were... » read more

Blog Review: Nov. 17


In a podcast, Arm's Geof Wheelwright and Hilary Tam chat about the importance of efforts to decarbonize compute and how low-power compute can help ensure that the benefits of technology outweigh the environmental cost. Synopsys' Graham Allan and Vikas Gautam consider what's driving demand for HBM3, what's different from the previous HBM2E specification, unique design considerations, and how ... » read more

1.6 Tb/s Ethernet Challenges


Moving data at blazing fast speeds sounds good in theory, but it raises a number of design challenges. John Swanson, senior product marketing manager for high-performance computing digital IP at Synopsys, talks about the impact of next-generation Ethernet on switches, the types of data that need to be considered, the causes of data growth, and the size and structure of data centers, both in the... » read more

Week In Review: Design, Low Power


Infineon reported fourth quarter 2021 financial results with revenue of €3.0 billion (~$3.4 billion), up 21% compared to the same quarter last year. For the full year, revenue was €11.1 billion (~$12.7 billion), an increase of 29% from the previous year. "In light of the continued high demand for semiconductors needed for the energy-efficient, connected world, we expect the 2022 fiscal year... » read more

Debugging Embedded Applications


Debugging embedded designs is becoming increasingly difficult as the number of observed and possible interactions between hardware and software continue to grow, and as more features are crammed into chips, packages, and systems. But there also appear to be some advances on this front, involving a mix of techniques, including hardware trace, scan chain-based debug, along with better simulation ... » read more

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