Week In Review: Design, Low Power

RISC-V models; developing chips for DoD; Renesas FPGA; Samsung tool certifications.


Imperas Software released updated simulator and reference models that support the latest RISC-V extensions for Bit Manipulation 1.0.0, Cryptographic (Scalar) 1.0.0, and Vector 1.0, plus Privilege Specification 1.12. They are offered both as freely available, open-source reference models for the RISC-V community as well as commercial products.

Ansys’ multiphysics signoff solutions were certified for Samsung Foundry’s 3nm and 4nm process technologies. The certification includes tools for power network extraction, power integrity and reliability, signal electromigration, thermal reliability analysis for self-heat, thermal-aware electromigration, and statistical electromigration budgeting.

Cadence’s Integrity 3D-IC platform was qualified by Samsung Foundry for to allow customers to partition existing 2D designs into 3D memory-on-logic configurations on the 5LPE design stack. The flow also provides 3D-IC system planning, implementation, and early analysis capabilities for the partitioned design.

Siemens Digital Industries Software said that tools including those targeting advanced packaging, electrostatic discharge rules, and IC design in the cloud were successfully evaluated for Samsung Foundry’s latest process technologies.

Synopsys’ full EDA flow was certified by Samsung Foundry for its new 4nm Low Power Plus (4LPP) process. In addition, Synopsys’ 3DIC Compiler 2.5D and 3D multi-die package co-design and co-analysis platform was validated for the Samsung Foundry Multi-Die Integration (MDI) flow.

Samsung Foundry used Cadence’s Liberate Trio Characterization Suite to deliver 3nm production libraries that meet the requirements for a range of application areas with reduced turnaround time and improved productivity versus previous nodes. Samsung Foundry also deployed Cadence’s Tempus Timing Signoff Solution with a new SPICE-accurate aging analysis capability for automotive, aerospace, consumer, mobile, and hyperscale design. Samsung noted it enabled better PPA and up to 4.2% improved frequency.

Realtek adopted Ansys’ electromagnetic (EM) simulation workflow to decrease simulation time for predicting EM coupling in applications ranging from RFIC and high-speed IC to IoT products.

The U.S. Department of Defense selected Microsoft to help lead the second phase of its Rapid Assured Microelectronics Prototypes (RAMP) using Advanced Commercial Capabilities project. The project aims to provide an advanced microelectronics development platform for mission-critical applications, and the second phase will focus on development of custom integrated chips and SoC designs using a secure, collaborative design flow. Other companies participating in the project include Ansys, Applied Materials, BAE Systems, Battelle Memorial Institute, Cadence, Cliosoft, Flex Logix, GlobalFoundries, Intel Federal, Raytheon Intelligence and Space, Siemens EDA, Synopsys, Tortuga Logic, and Zero ASIC Corporation.

The Silicon Integration Initiative (Si2) launched the Technology Interoperability Trajectory Advisory CouNcil (TITAN), which will work with Si2 member companies to explore a spectrum of technology interoperability gaps between EDA suppliers, cloud providers, foundries, semiconductor, and emerging silicon-to-system companies. “The primary goal for TITAN is to accelerate innovation through industry collaboration to achieve faster time to results and time to market,” said Vic Kulkarni, Si2 chief strategy officer. “TITAN will serve as the trusted technology advisor to the Si2 board of directors, which evaluates and forwards proposals to Si2 technology teams for prioritization and action plans. Council members will determine the best path forward for industry collaboration and commit resources to develop and prototype gap technologies.”

Functional safety & security
Arteris IP launched the Harmony Trace Design Data Intelligence Solution to ease compliance with semiconductor industry functional safety and quality standards such as ISO 26262, IEC 61508, ISO 9001, and IATF 16949. Implemented as an enterprise-level server-based application with a web-based UI, it aims to increase system quality and accelerate functional safety assessments by identifying and fixing the traceability gaps between disparate systems.

Intrinsic ID and Rambus teamed up to combine Intrinsic ID’s physical unclonable function (PUF) technology with Rambus Root of Trust security cores. The IP uses the inherently random start-up values of SRAM as a PUF, which generates the entropy required for the hardware Root of Trust.

Infineon extended the tools and graphical support available for PSoC 6 MCUs, adding the Embedded Wizard Studio. “Designers now have a larger set of software tools to support high-performance graphics for their PSoC 6 MCU applications with Embedded Wizard,” said Danny Watson, Principal Software Product Marketing Manager at Infineon. It enables GUIs that can be deployed for voice and graphics targeting IoT applications such as wearables and white appliances.

Renesas entered the FPGA market with a line of low-cost, low-power devices. The ForgeFPGA Family will serve applications that require less than 5,000 gates of logic, with initial device sizes of 1K and 2K LUTs. Standby power of less than 20 microamps is projected for the first devices, with development software available for both new and experienced FPGA designers.

CAST and Beyond Semiconductor uncorked a new RISC-V low-power embedded processor IP core. Implementing a two-stage pipeline, the 32-bit core has 16k gates in its minimum configuration and targets applications where fast interrupt response is necessary.

Lattice Semiconductor acquired Mirametrix, a software company that focuses on AI for computer vision applications. “Adding Mirametrix’s proven AI and computer vision software to our existing solution stack portfolio will make it even easier for our customers to quickly add more intelligence to their applications,” said Jim Anderson, Lattice Semiconductor President and CEO. Terms of the deal were not disclosed.

Infineon introduced the OptiMOS 6 100 V family of power MOSFETs. They are optimized for high switching frequency applications such as telecom and solar, as well as battery-powered applications and battery management systems.

Data center, HPC, quantum
Xilinx unveiled a data center accelerator card along with a new standards-based, API-driven clustering solution for deploying FPGAs at massive scale. The Alveo U55C accelerator card is a single-slot full height, half length form factor with 150W max power and includes 16GB HBM2.

IBM revealed a new 127-qubit processor. Called Eagle, the processor has a qubit arrangement design to reduce errors and an architecture to reduce the number of necessary components. New techniques used place control wiring on multiple physical levels within the processor while keeping the qubits on a single layer, which enables a significant increase in qubits. IBM said that the number of qubits make it impossible to reliably simulate on classical hardware. It can be accessed through IBM Cloud. The company also announced its upcoming Quantum System Two, which will use a modular architecture and incorporate a new generation of scalable qubit control electronics together with higher-density cryogenic components and cabling. It will use IBM’s future 433-qubit and 1,121 qubit processors.

The Fugaku supercomputer continues to hold the top spot in the latest edition of the Top500 supercomputer rankings. Built by Riken and Fujitsu and based on Fujitsu’s custom ARM A64FX processor, it reached an HPL benchmark score is 442 Pflop/s, exceeding the number two system, Oak Ridge National Laboratory’s Summit, by 3x. The only new system to reach the top ten was the Microsoft Azure system called Voyager-EUS2, which is based on an AMD EPYC processor with 48 cores and 2.45GHz working together with an NVIDIA A100 GPU and 80 GB of memory and utilizing a Mellanox HDR Infiniband for data transfer.

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