Blog Review: May 8

By Jesse Allen - 08 May, 2024 - Comments: 0

Synopsys' Manuel Mota and Michael Posner look to UCIe as a complete stack for the die-to-die interconnect in multi-die chip designs, finding it can help maintain latency while reducing power and enhancing performance along with providing assurance of interoperability. Cadence's Durlov Khan highlights the Octal SPI interface for serial NAND flash, which enables 8-bit wide high bandwidth synch... » read more

Communication Is Key To Finding And Fixing Bugs In ICs

By Ann Mutschler and Adam Kovac - 08 May, 2024 - Comments: 0

Experts at the Table: Finding and eliminating bugs at the source can be painstaking work, but it also can prevent even greater problems from developing later on. To examine the best ways to tackle this problem, Semiconductor Engineering sat down with Ashish Darbari, CEO at Axiomise; Ziyad Hanna, corporate vice president R&D at Cadence; Jim Henson, ASIC verification software product manager ... » read more

Can Models Created With AI Be Trusted?

By Brian Bailey - 06 May, 2024 - Comments: 0

EDA models that are created using AI need to pass more stringent quality and cost benefit analysis compared to many AI applications in the broader industry. Money is hanging on the line if AI gets it wrong, and all the associated costs must be factored into the equation. Models are some of the most expensive things a development team can create, and it is important to understand the value th... » read more

Blog Review: May 1

By Jesse Allen - 01 May, 2024 - Comments: 0

Cadence's Vatsal Patel stresses the importance of having testing and training capabilities for high-bandwidth memory to prevent the entire SoC from becoming useless and points to key HBM DRAM test instructions through IEEE 1500. In a podcast, Siemens' Stephen V. Chavez chats with Anaya Vardya of American Standard Circuits about the growing significance of high density interconnect and Ultra ... » read more

Multi-Die Design Pushes Complexity To The Max

By Ann Mutschler - 29 Apr, 2024 - Comments: 1

Multi-die/multi-chiplet design has thrown a wrench into the ability to manage design complexity, driving up costs per transistor, straining market windows, and sending the entire chip industry scrambling for new tools and methodologies. For multiple decades, the entire semiconductor design ecosystem — from EDA and IP providers to foundries and equipment makers — has evolved with the assu... » read more

EDA Looks Beyond Chips

By Ed Sperling - 25 Apr, 2024 - Comments: 0

Large EDA companies are looking at huge new opportunities that reach well beyond semiconductors, combining large-scale multi-physics simulations with methodologies and tools that were developed for chips. Top EDA executives have been talking about expanding into adjacent markets for more than a decade, but the broader markets were largely closed to them. In fact, the only significant step in... » read more

Dealing With AI/ML Uncertainty

By Karen Heyman - 25 Apr, 2024 - Comments: 0

Despite their widespread popularity, large language models (LLMs) have several well-known design issues, the most notorious being hallucinations, in which an LLM tries to pass off its statistics-based concoctions as real-world facts. Hallucinations are examples of a fundamental, underlying issue with LLMs. The inner workings of LLMs, as well as other deep neural nets (DNNs), are only partly kno... » read more

Is There Any Hope For Asynchronous Design?

By Brian Bailey - 25 Apr, 2024 - Comments: 6

In an era when power has become a fundamental design constraint, questions persist about whether asynchronous logic has a role to play. It is a design style said to have significant benefits and yet has never resulted in more than a few experiments. Synchronous design utilizes a clock, where the clock frequency is set by the longest and slowest path in the design. That includes potential var... » read more

Revitalizing DAC

By Brian Bailey - 25 Apr, 2024 - Comments: 0

The 61st Design Automation Conference is just two months away and as I get closer to retirement, I know there will only be a few remaining for me. I entered the EDA industry in 1980, so have been involved with it for almost 45 years. Over that period, I have only missed a few. It is interesting how the conference has changed over the years. In the early days, DAC was only a conference, where... » read more

The 3D-IC Multiphysics Challenge Dictates A Shift-Left Strategy

By John Ferguson - 25 Apr, 2024 - Comments: 0

As the industry marches forward in a 3D-IC centric design approach (figure 1), we are facing a new problem. Sometimes referred to as “electro-thermal” or “electro-thermo-mechanical,” it really is the confluence of multiple forms of physics exerting impacts on both the physical manufacture and structure of these multi-die designs and their electrical behavior. Fig. 1: Illustration... » read more

← Older posts Newer posts →

Knowledge Centers
Entities, people and technologies explored

Shift Left Is The Tip Of The Iceberg

A transformative change is underway for semiconductor design and EDA. New languages, models, and abstractions will need to be created.

by Brian Bailey

Partitioning In The Chiplet Era

Understanding how chiplets interact under different workloads is critical to ensuring signal integrity and optimal performance in heterogeneous designs.

by Ann Mutschler

3.5D: The Great Compromise

Pros and cons of a middle-ground chiplet assembly that combines 2.5D and 3D-IC.

by Ed Sperling

AI’s Role In Chip Design Widens, Drawing In New Startups

Focus is on letting engineers do much more with the same or fewer resources — and less drudgery.

by Karen Heyman

What Comes After HBM For Chiplets

The standard for high-bandwidth memory limits design freedom at many levels, but that is required for interoperability. What freedoms can be taken from other functions to make chiplets possible?

by Brian Bailey

Memory Fundamentals For Engineers

eBook: Nearly everything you need to know about memory, including detailed explanations of the different types of memory; how and where these are used today; what's changing, which memories are successful and which ones might be in the future; and the limitations of each memory type.

by The SE Staff

Why Small Fab And Assembly Houses Are Thriving

Megafabs churning out the most advanced processors are not the only game in town.

by Bryon Moyer

New AI Processors Architectures Balance Speed With Efficiency

Hot Chips 24: Large language models ratchet up pressure for sustainable computing and heterogeneous integration; data management becomes key differentiator.