category: System-Level Design

category: Auto, Security & Edge AI

FPGAs Find New Workloads In The High-Speed AI Era
By Liz Allan - 25 Nov, 2025 - Comments: 0

FPGAs are finding new applications in the age of artificial intelligence, high-speed wireless communications, medical and life science technology, and in complex chip architectures where they can improve the flow of data. Field-programmable gate arrays (FPGAs) enable designers to reprogram or reconfigure digital logic after the chips have been deployed, which is essential in the AI world, wher... » read more

Shaping The Future Of AI Processors: A Tech Threads Conversation With Jim Keller
By Nandan Nayampally - 25 Nov, 2025 - Comments: 0

I had the pleasure of hosting renowned computer architect and Tenstorrent CEO Jim Keller, on the latest episode of Baya Systems’ Tech Threads podcast. If you haven’t already, listen to get his insights on the need for “open” intelligence architectures and what would be needed to drive the semiconductor industry forward. What is an “open” intelligent architecture and ecosystem? As... » read more

Securing IP Integrity In Advanced SoC Design
By Sara Khalaf - 25 Nov, 2025 - Comments: 0

In today’s complex system-on-chip (SoC) design flows, intellectual property (IP) blocks are everywhere—licensed from third parties, leveraged from internal libraries, or hand-crafted by expert teams. These IPs are typically delivered in a “black box” format and are expected to remain unchanged throughout the physical design stages, from initial floorplanning to top-level placement, rout... » read more

The Real-World Impact Of Silicon Lifecycle Management On Chip Architectures
By Ann Mutschler - 25 Nov, 2025 - Comments: 0

Silicon lifecycle management (SLM) is transforming chip architectures, empowering designers to build smarter, more resilient, and secure semiconductor devices by leveraging data from manufacturing to end of life in the field. That data can be used to improve future designs, reduce margin, and continuously optimize performance and power efficiency throughout a chip's lifetime. Moreover, under... » read more

A Golden Source As The Single Source Of Truth In HSI
By Tim Schneider - 25 Nov, 2025 - Comments: 0

The hardware/software interface (HSI) is where system-on-chip (SoC) software defines the connections between the software and the underlying hardware. Maintaining a precise, synchronized HSI across all artifacts is challenging, and unmanaged deviations can propagate through the flow and affect integration schedules. Most complex SoCs rely on IP reuse, each with its own naming conventions, ha... » read more

What Is 3D-IC Technology? Fundamentals, Architecture, And Design Concepts
By Reela Samuel - 25 Nov, 2025 - Comments: 0

As process nodes continue to advance into the sub-micron era, the limitations of traditional scaling are becoming increasingly evident. Larger monolithic chips are facing challenges such as higher power density, routing congestion, and reduced yield. Three-dimensional integrated circuits (3D-IC) technology represents a breakthrough approach by stacking multiple dies vertically. This design red... » read more

Guarantee IP Integrity With Calibre IP Checker
By Siemens EDA - 25 Nov, 2025 - Comments: 0

In complex SoC designs, intellectual property (IP) blocks are critical yet vulnerable. Unintended modifications to IP during placement, routing or fill stages often go undetected by traditional DRC, leading to functional failures, performance degradation and costly re-spins. This paper introduces Calibre IP Checker, an automated, shift-left solution designed to guarantee IP integrity. It works ... » read more

PCI Express Design Guide – Q&A for Gen 4, 5, 6
By Cadence - 24 Nov, 2025 - Comments: 0

High-speed PCB design for PCI Express Gen4, Gen5, and Gen6 pushes every dimension of signal integrity and layout engineering. This PCIe Design Guide – Q&A (Part 1) compiles 60 of the most common real-world design questions that engineers face—and provides detailed, practical answers grounded in simulation data, field experience, and compliance testing. Whether you’re defining your... » read more

Faster Bug Discovery And Coverage Closure
By Synopsys - 24 Nov, 2025 - Comments: 0

Modern chip development is a complex process where functional verification often consumes a significant portion of project time and resources. Achieving efficient bug discovery and coverage closure is essential to prevent issues from reaching silicon. This white paper introduces an innovative approach using AI-powered Verification Space Optimization (VSO.ai) to enhance verification processes. ... » read more

Spray And Pray Wastes Power
By Brian Bailey - 24 Nov, 2025 - Comments: 0

For quite some time I have felt that the way the industry approaches power is less than optimal. Techniques such as clock gating and power gating have been used to reduce the amount of unnecessary activity and leakage, but is there more activity that does not contribute to an intended action? While unnecessary activity may be unimportant in the functional sense, it all represents power that ... » read more

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