Anatomy Of A System Simulation


The semiconductor industry has greatly simplified analysis by consolidating around a small number of models and abstractions, but that capability is breaking down both at the implementation level and at the system level. Today, the biggest pressure is coming from the systems industry, where the electronic content is a small fraction of what must be integrated together. Systems companies tend... » read more

System-on-Chip Integration Complexity And Hardware/Software Contracts


From the earliest days of my career, when designing chips, I have always navigated the interface between hardware and software for semiconductor design in my roles. My initial chip designs included video and audio encoding and decoding, supporting standards like MPEG and H.261. As acceleration parts of hardware/software systems, these had many Control and Status Registers (CSRs) to program. The... » read more

Rethinking Design, Workflow For 3D


In the 3D world, where NAND has hundreds of layers and packages come in intricate stacks, fresh graduates and veteran engineers alike are being confronted with design challenges that require a rethinking of both classic designs and traditional workflows, but without breaking the laws of physics. “There are pockets of things that have been on 3D for quite some time,” said Kenneth Larson, ... » read more

Leaps in Quantum Computing


There are new computers that are generating some amazing results for solving problems in record time.  You won’t see these computers on the classic Top500 lists though, because they aren’t approaching computing in the same way. Using quantum computing algorithms like Shor’s algorithm for factoring large numbers, quantum computing holds the promise of solving problems that take exponentia... » read more

Causes Of Memory Unsafety


Memory unsafety is a characteristic of many of today’s systems. The root cause of buffer bounds vulnerabilities such as buffer overflows and over-reads is unsafe programming. Major software vendors consistently report memory unsafety problems. For example, the Chromium open-source browser project has stated that 69% of CVEs (Common Vulnerabilities and Exposures) reported relate to memory... » read more

Making Connections In 3D Heterogeneous Integration


Activity around 3D heterogeneous integration (3DHI) is heating up, driven by growing support from governments, the need to add more features and compute elements into systems, and a widespread recognition that there are better paths forward than packing everything into a single SoC at the same process node. The leading edge of chip design has changed dramatically over the last few years. Int... » read more

AI For Circuit Design Quality, Productivity, And Advanced-Node Mapping


The future of circuit design, encompassing analog, RF/5G, and custom electronic circuits, is set to be revolutionized by the integration of generative AI tools. These advanced tools will not only enhance the quality of designs and boost designer productivity but also facilitate the mapping of designs from older semiconductor process nodes to more advanced nodes such as 3nm and below. This blog ... » read more

Let’s Do The (IC Design) Time Warp Again


For the most part, we’ve all been doing integrated circuit (IC) and system-on-chip (SoC) layout the same way for decades. Designers put together the design, be it intellectual property (IP), block, or full chip, then begin running physical verification. For design rule checking (DRC), this process consists of running all appropriate rule checks for the component on all available layouts. The ... » read more

Powering Up Electric Heavy-Duty Vehicles


Smokey tailpipe emissions may soon be a thing of the past, as the heavy transport vehicle market catches up with the electric car market to lower their contribution to greenhouse gas (GHG) emissions. Private sedans and light-duty trucks lead the vehicle electrification race, leaving much upside opportunity for heavy transport fleets such as trucks and buses to catch up. In the United Stat... » read more

Navigating EDA Vendor Cloud Options


Experts at the Table: Semiconductor Engineering sat down to discuss the challenges of cost-dependent cloud decisions, and how to navigate between different EDA vendor clouds options with Philip Steinke, fellow, CAD infrastructure and physical design at AMD; Mahesh Turaga, vice president of business development for cloud at Cadence Design Systems; Richard Ho, vice president hardware engineering ... » read more

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