category: System-Level Design

category: Auto, Security & Edge AI

Streamlining Functional Verification For Multi-Die And Chiplet Designs
By Cadence - 30 Jul, 2025 - Comments: 0

An Opportunity and a Challenge The manufacturing aspects of multi-die/multi-chiplet designs are often highlighted, but what about verification? Functional correctness and performance of inter-die connections via a standard interface, such as UCIe or a custom inter-die interface, are not guaranteed to meet all system requirements. These interfaces must be verified comprehensively, ensuring co... » read more

Blog Review: July 30
By Jesse Allen - 30 Jul, 2025 - Comments: 0

Siemens' John McMillan compares 2.5D and 3D-IC technologies and why choosing between them depends on the specific requirements of a product, such as power consumption, thermal constraints, form factor limitations, data bandwidth, and performance-per-watt targets. Cadence's Yeshavanth BN checks out changes in MIPI MPHY 6.0 that increase the data rate and improve the performance of next-genera... » read more

CodaCache Last-Level Cache IP
By Arteris - 30 Jul, 2025 - Comments: 0

CodaCache Last-Level Cache (LLC) IP, is a configurable, standalone cache designed to enhance system performance, data locality, scalability, power efficiency, and cost-effectiveness in system-on-chip (SoC) designs. It aims to optimize data sharing among computing engines, accelerators, and data processing blocks by improving prefetching mechanisms to lessen reliance on main memory, thereby enha... » read more

Navigating The Quantum Revolution In A Year Of Transformation
By Keysight - 30 Jul, 2025 - Comments: 0

In 2025, which the United Nations has designated as the International Year of Quantum Science and Technology, business leaders face a transformative moment where quantum computing emerges from research labs into commercial applications, which early adopters already demonstrating quantum advantage in practical scenarios. This white paper explores how quantum technologies are revolutionizing key ... » read more

Accelerating IP Reuse
By Ed Sperling - 23 Jul, 2025 - Comments: 0

Semiconductors are no longer monolithic designs developed by a single company. There is more third-party IP from different sources — as many as 1,000 different IPs in a complex SoC — and all of that needs to be integrated and work as one system, something that can require a lot of effort and time. Insaf Meliane, product management and marketing director at Arteris, talks about how the new v... » read more

Blog Review: July 23
By Jesse Allen - 23 Jul, 2025 - Comments: 0

Synopsys' Vincent van der Leest and Mike Borza argue that hardware security is critical for providing the foundational trust, physical protection, and performance enhancements necessary to support software security and prevent leaks of sensitive data and cryptographic keys. Siemens' Shetha Nolke explains why stress matters so much in 3D-ICs and why evaluating it isn't as straightforward as i... » read more

Questa One Avery VIP: Accelerated Confidence In Complex Protocol Verification
By Siemens EDA - 21 Jul, 2025 - Comments: 0

In today’s rapidly advancing digital landscape, the role of functional verification has never been more critical. As systems become increasingly complex, ensuring their reliability and performance poses significant challenges for both design and verification engineers. The stakes are high; verification failures can lead to costly recalls, safety risks, and damage to brand reputation. The late... » read more

Blog Review: July 16
By Jesse Allen - 16 Jul, 2025 - Comments: 0

Synopsys' Bradley Geden and Manoz Palaparthi explain the difference between functional signoff and RTL signoff and why increased SoC complexity means that verification flows must now capture both the intent and the integrity of a design before it can move forward. Cadence's Frank Ferro finds that LPDDR isn't just for mobile devices anymore, with the new LPDDR6 standard bringing increased ban... » read more

AI In Chip Design: Tight Control Required
By Ed Sperling - 16 Jul, 2025 - Comments: 0

Executive Outlook: Semiconductor Engineering sat down with a panel of experts to talk about what's needed to effectively leverage AI, who benefits from it, and where software-defined hardware works best, with Bill Mullen, Ansys fellow; John Ferguson, senior director of product management at Siemens EDA; Chris Mueth, senior director of new markets and strategic initiatives at Keysight; Albert Ze... » read more

Silicon IP Revenue Spikes
By Ed Sperling - 15 Jul, 2025 - Comments: 0

EDA and silicon IP revenue grew 12.8% in Q1 2025, totaling $5.098 billion compared to $4.522 billion in the same period last year, but the real story was on the IP side, surging 29.6% year-over-year to $1.577 billion. Drilling deeper into those numbers, revenue for non-reporting IP companies — predominantly Arm — jumped 34.1% YoY to $1.031 billion. That was positive news for the IP marke... » read more

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