Blog Review: July 23

Synopsys’ Vincent van der Leest and Mike Borza argue that hardware security is critical for providing the foundational trust, physical protection, and performance enhancements necessary to support software security and prevent leaks of sensitive data and cryptographic keys.

Siemens’ Shetha Nolke explains why stress matters so much in 3D-ICs and why evaluating it isn’t as straightforward as it may seem, given the interplay of mechanical and electrical effects that require the combined ingenuity of chip designers, packaging teams, and process experts.

Cadence’s Shu Wang explores the data encryption and integrity protection features available in CXL 3.x, including the introduction of an IDE termination handshake, which facilitates a coordinated shutdown of the CXL.CacheMem IDE between the transmitter and receiver.

Arm’s Michalis Spyrou introduces a project that uses LLMs to assist in security code review to unveil subtle logic flaws or design inconsistencies that aren’t always visible to traditional rule-based static application security testing tools.

Ansys’ Emily Gerken shows how multiphysics simulation can improve parasitic extraction by locating electromagnetic issues that are not otherwise intuitively evident and are too complex for hand calculations.

Keysight’s Roberto Piacentini Filho shares several tips for overcoming signal and power integrity challenges in modern high-speed systems using simulation.

SEMI’s Jaegwan Shim highlights future materials and processes for 3D DRAM and CFET devices, technical barriers facing HBM, and a positive outlook for the materials market.

And don’t miss the blogs featured in the latest Low Power-High Performance newsletter:

Technology strategy advisor Geoff Tate considers that while AMD is close to surpassing Intel in x86, Arm thinks it can take the lead over x86.

Expedera’s Paul Karazuba examines the new challenges introduced with complex model architectures, demanding runtime computations, and transformer-specific operations.

Fraunhofer’s Andy Heinig finds that a full-fledged chiplet ecosystem will require much more than just standardized die-to-die interfaces.

Synopsys’ Bradley Geden and Manoz Palaparthi explain why increased SoC complexity requires verification flows to capture both the intent and integrity of a design.

Rambus’ Lou Ternullo promotes the need for flexibility to support composability in high-speed interconnects.

Quadric’s Steve Roddy contends that rapid innovation in transformer networks has rendered the simple offload NPU obsolete.

Siemens’ Andras Vass-Varnai, Lee Wang, John Parry, Byron Blackmore, and Sudarshan Deo look to automated workflows to bridge the gap between electrical/package design and thermal analysis in stacked die.

Cadence’s Reela Samuel argues that a dedicated computing infrastructure is needed to oversee the complete AI life cycle.

Ansys’ Sanjay Angadi and Matteo Nicolich look at the potential impact of one design change on other parts of a design.

Arm blogger Peter Ma digs into unpredictable cloud CPU costs when scaling ML inference.