CSR Management: Life Beyond Spreadsheets


The ASIC, ASSP, and system-on-chip (SoC) design landscape has undergone significant evolution over the past two decades. For example, while early devices contained only tens of intellectual property (IP) blocks, modern high-end SoCs may integrate up to 1000 IPs, each containing millions of logic gates. Furthermore, unlike their predecessors, today’s SoCs are no longer primarily hardware; i... » read more

Optical Interconnectivity At 224 Gbps


AI is generating so much traffic that traditional copper-based approaches for moving data inside a chip, between chips, and between systems, are running out of steam. Just adding more channels is no longer viable. It requires more power to drive signals, and the distance those signals can travel without excessive loss is shrinking. Mike Klempa, product marketing specialist at Alphawave Semi, di... » read more

SoC Power Delivery Network (PDN) Telemetry And Applications


PDN characterization needs visibility at the transistor. Through this white paper, we will learn why PDN visibility is crucial to each stage of the silicon lifecycle and its relation to power, performance, and in-field uptime. Register here to download the paper. » read more

AI Infrastructure: Optimized For Model Training


This white paper discusses the critical infrastructure needed for efficient AI model training, emphasizing the role of network capabilities in handling vast data flows and minimizing delays. It outlines challenges in model training and innovative solutions that can enhance performance. AI Revolution: The increasing complexity of AI applications, such as autonomous vehicles and personalized m... » read more

Mastering AI Chip Complexity: Your Guide to First-Pass Silicon Success


This eBook provides a resource for innovators in the fast-changing realm of AI chip development. It delves into the opportunities and challenges of designing cutting-edge AI chips and chiplets, focusing on the transition from traditional monolithic architectures to multi-die and chiplet-based solutions. The content covers essential topics such as architectural exploration, silicon design, a... » read more

Blog Review: May 28


Siemens’ Patrick Hope considers how to fully perform post-route signal integrity verification on PCB designs while maintaining the project’s timeline by implementing a progressive verification methodology that enables signal integrity experts to focus on issues that demand their expertise rather than simple errors. Cadence’s Vanessa Do checks out how CXL addresses the constant demand f... » read more

Modernizing The Hardware / Software Interface – Life Beyond Spreadsheets


The hardware/software interface (HSI) is the core of advanced semiconductor design, allowing seamless interaction between software and components like accelerators and peripherals. It underpins critical functions such as documentation, firmware, and hardware verification. Inefficient or outdated HSI management reduces collaboration, increases design errors, and threatens the performance and qua... » read more

Agentic AI, Multi-Block Multi-User SoC Design Platform


The semiconductor industry is at an inflection point within its history. The latest technological advancements in AI, quantum computing, 5G, virtual and augmented reality, IoT, autonomous driving, and biotechnology have revolutionized the semiconductor industry. The growing demands of AI workloads and sophisticated model training are spurring highly specialized semiconductor chips with intricat... » read more

Blog Review: May 21


Synopsys’ Frank Malloy listens in on a panel discussing the engineering challenges introduced by multi-die designs, from multi-physics interactions that impact power and thermal integrity to the availability of multi-die packages and industry standards. Siemens’ Bruce Caryl shows how to determine how much a design’s power delivery network is contributing to jitter on the output drivers... » read more

More Data, More Redundant Interconnects


The proliferation of AI dramatically increases the amount of data that needs to be processed, stored, and moved, accelerating the aging of signal paths through which that data travels and forcing chipmakers to build more redundancy into the interconnects. In the past, nearly all redundant data paths were contained within a planar chip using a relatively thick silicon substrate. But as chipma... » read more

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