Blog Review: Aug. 6

Cadence’s Shyam Sharma checks out key features of the LPDDR6 specification, including data transfer speeds that can reach up to 14.4Gbps, two sub-channels per device, metadata built into the data packets, and row hammer mitigation.

Synopsys’ Frank Malloy and Vincent van der Leest describe the essential role that a hardware root of trust plays in providing a secure foundation for all other security operations within a system and ensuring that even in the presence of potential vulnerabilities, the system can operate in a trusted environment.

Siemens’ Bill Hargin presents an introduction to digital crosstalk in PCBs, including various design rules for controlling edge coupled signal-to-signal crosstalk and which design tweaks provide the most leverage for controlling far-end crosstalk.

Keysight’s Roberto Piacentini Filho argues that structured, contextualized, and accessible design data is key to unlocking the full potential of the semiconductor development process, from smarter reuse to predictive verification and generative layout.

Ansys’ Jayraj Nair warns that traditional simulation approaches that treat electrical, thermal, and mechanical phenomena separately aren’t up to the complexity of heterogeneous multi-die systems, which require that multiple domains be analyzed holistically.

Arm’s John Thompson finds the IoT edge computing landscape is shifting, with a growing number of IoT engineers planning to adopt open-source operating systems within three years and the use of NPUs expected to nearly double.

In a blog for SEMI, Lam Research’s Sara Turner and Teradyne’s Mike Halblander introduce guidance to help semiconductor companies across the supply chain calculate and report emissions stemming from how their products are used.

And don’t miss the blogs featured in the latest Systems & Design newsletter:

Technology editor Brian Bailey considers what we can learn from hallucinations, and where AI will fit into the chip design flow.

Siemens’ Paul Carpine suggests it’s time to reassess the optimal temperature for electronics manufacturing facilities.

Cadence’s Krunal Patel shows how link-layer retry can fix packet loss locally and avoid expensive recovery mechanisms.

Arteris’ Insaf Meliane examines how a structured approach can ensure consistent IP metadata representation across abstraction levels, design tools, and development teams.

Keysight’s Richard Duvall looks at how new optimizer algorithms can impact increasingly complex RF chip designs.

Synopsys’ Manoz Palaparthi explains why parallelized, hierarchical, and distributed timing analysis are necessary for HPC and AI chips.