category: System-Level Design

category: IoT, Security & Automotive

Artificial Intelligence Wonderland
By Barry Pangrle - 30 Nov, 2023 - Comments: 0

Silicon Catalyst held its Sixth Annual Semiconductor Forum in Menlo Park on the SRI campus on November 9th. Richard Curtin, Managing Partner for Si Catalyst, opened the event with a reference to Arthur C. Clarke’s "2001: A Space Odyssey" and noted how remarkable it was that a novel written back in 1968 was able to foretell the direction of the computer industry over 50 years into the future. ... » read more

SoC Integration And Data Transport Architecture Requirements Surge In 2023
By Frank Schirrmeister - 30 Nov, 2023 - Comments: 0

As the holiday season is in full swing, it's retrospection and prediction time! Let's look at what I thought 2023 would look like, review how it turned out, and take a first stab at 2024 predictions. As a spoiler, my biggest surprise was the intensity with which artificial intelligence and machine learning (AI/ML) accelerated since Generative AI was put on the mainstream adoption map last year,... » read more

Successful 3D-IC Design, Verification, And Analysis Requires An Integrated Approach
By Siemens EDA - 30 Nov, 2023 - Comments: 0

3D-IC designs enable improvements in performance, power, footprint, and costs that cannot be attained in system-on-chip (SoC) and IC design. However, the leap from traditional SoC/IC design to 3D-IC designs brings not only new opportunities, but also new challenges. Siemens EDA provides multiple 3D-IC design analysis and verification functionalities that address the diverse needs of 3DIC des... » read more

Building Tomorrow’s Electronics Piece By Piece
By Reela Samuel - 30 Nov, 2023 - Comments: 0

The semiconductor landscape is undergoing a seismic shift as the demand for more powerful and energy-efficient electronic devices reaches new heights. In a recent panel discussion at CadenceLIVE Europe, featuring luminaries such as Kevork Kechichian from Arm, Paul Cunningham from Cadence, Norbert Schuhmann from Fraunhofer, Trent Uehling from NXP, Davide Rossi from the University of Bologna, an... » read more

Accelerate 5G Testing
By Keysight - 29 Nov, 2023 - Comments: 0

The promise of 5G is faster and more reliable communications. To enable mobile broadband communications, 5G uses existing and new technologies to achieve extreme data throughputs. In this white paper, you will learn about the impact of the 3GPP evolution on your testing and solutions available to help you scale to production quickly. Click here to read more. » read more

Blog Review: November 29
By Jesse Allen - 29 Nov, 2023 - Comments: 0

Siemens' Matt Walsh checks out electro-thermal design and how a Boundary Condition Independent Reduced Order Model (BCI-ROM) can capture accurate characteristics from a 3D thermal analysis, ready for use in a 1D circuit simulation. Cadence's Vinod Khera considers how EDA could benefit from the AI revolution by providing a productivity boost through virtual assistants and improving code quali... » read more

The Evolution Of RISC-V Processor Verification: Open Standards And Verification IP
By Imperas - 29 Nov, 2023 - Comments: 0

The OpenHW Group’s [1] Verification task group has been a pioneer in the development of methodologies and verification collateral for RISC-V processor verification. Since 2019 the members have worked together to develop CORE-V-VERIF: a UVM environment for the verification of RISC-V processor cores. Over this period of time the CORE-V-VERIF environment has evolved as new processor verification... » read more

Improving AI Productivity With AI
By Ed Sperling - 28 Nov, 2023 - Comments: 0

AI is showing up or proposed for nearly all aspects of chip design, but it also can be used to improve the performance of AI chips and to make engineers more productive earlier in the design process. Matt Graham, product management group director at Cadence, talks with Semiconductor Engineering about the role of AI in identifying patterns that are too complex for the human brain to grasp, how t... » read more

What To Do About Electrostatic Discharge
By Ed Sperling - 20 Nov, 2023 - Comments: 0

Electrostatic discharge is a well-understood phenomenon, but it’s becoming more difficult to plan for as single chips are replaced by multiple chips or chiplets in a package, and as the density of components continues to increase with each new node. In both cases, the probability for failure increases unless these sudden shocks are addressed in the design. Dermott Lynch, director of product m... » read more

Blog Review: November 15
By Jesse Allen - 15 Nov, 2023 - Comments: 0

Cadence's Neelabh Singh explores the process of lane initialization and link training in bringing up a high-speed link in USB4. Synopsys' Shela Aboud argues that TCAD should be an integral part of an EDA flow as it enhances design technology co-optimization with a way to experiment and determine what works and what doesn’t work at different process nodes using physics-based models. Siem... » read more

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