Blog Review: March 16


Ansys' Peter Hallschmid and Sandra Gely look at why, compared to rain and fog, snow is a different challenging environment for automotive sensors and how the random pattern of snowfall, properties of each flake, and the various distance between flakes play havoc on detecting objects. Siemens' Chuck Battikha focuses on how to protect against random hardware faults, the added costs of includin... » read more

Week In Review: Design, Low Power


Intellectual Property Flex Logix inked an agreement with the Air Force Research Laboratory, Sensors Directorate (AFRL/RY) covering any Flex Logix IP technology for use in all US Government-funded programs for research and prototyping purposes with no license fees. “Our first license with AFRL for EFLX eFPGA in GlobalFoundries 12nm process was highly successful, with more than a half dozen pr... » read more

Parasitic Characterization Comes To Power Design Simulation


Two power design challenges are taking teams into unfamiliar territory. Wide bandgap (WBG) semiconductors target greater efficiency and density. Stricter EMI compliance regulations now come standard in mission-critical industries. Power design practices are still catching up. Simulation often takes a back seat to respinning hardware prototypes until success. What’s missing that could make sim... » read more

Who Will Own Debug?


Recently, I had an interesting conversation with a verification leader of one of the world’s leading semiconductors companies. He has some 150 verification engineers in his organization and the group has been exploring EDA solutions for many years. While we’ve exchanged many ideas about EDA and innovation, one sentence that he said stays in my head: Whoever will own debug, will own th... » read more

Blog Review: March 9


Arm's Ajay Joshi investigates how to select the right benchmark for CPUs used in the Home device market, such as digital television and set-top box/over-the-top devices. Ansys' Jon Kordell checks out how reliability physics simulations and physical component characterization can support component swapping in high-reliability applications when the original part is unavailable due to supply ch... » read more

Week In Review: Design, Low Power


Tools & IP Imperas Software introduced the RISC-V Verification Interface (RVVI). The open standard and methodology can be adapted to any configuration permitted within the RISC-V specifications. RVVI defines interfaces between RTL, reference model, and testbench for RISC-V design verification, with the aim of making RISC-V processor DV reusable. It supports multi-hart, superscalar, and out... » read more

Preparing For Test Early In The Design Flow


Until very recently, semiconductor design, verification, and test were separate domains. Those domains have since begun to merge, driven by rising demand for reliability, shorter market windows, and increasingly complex chip architectures. In the past, products were designed from a functional perspective, and designers were not concerned about what the physical implementation of the product ... » read more

Blog Review: March 2


Arm's Charlotte Christopherson checks out SpiNNaker1, a project to develop a massively parallel, manycore supercomputer architecture that mimicked the interactions of biological neurons, and its follow up, SpiNNaker2, a hybrid system that combines statistical AI and neuromorphic computing. Cadence's Paul McLellan looks at open and generic PDKs that can be used by researchers and in education... » read more

Week In Review: Design, Low Power


Tools & IP Codasip debuted two new customizable low power embedded RISC-V processor cores. To support embedded AI applications, the L31/L11 cores run Google’s TensorFlowLite for Microcontrollers. Codasip Studio tools can be used to customize for specific system, software, and application requirements. Licensing the CodAL description of a Codasip RISC-V core grants customers a full archit... » read more

Data Center Architectures In Flux


Data center architectures are becoming increasingly customized and heterogeneous, shifting from processors made by a single vendor to a mix of processors and accelerators made by multiple vendors — including system companies' own design teams. Hyperscaler data centers have been migrating toward increasingly heterogeneous architectures for the past half decade or so, spurred by the rising c... » read more

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