category: System-Level Design

category: Auto, Security & Edge AI

Blog Review: Dec. 20
By Jesse Allen - 20 Dec, 2022 - Comments: 0

Synopsys' Twan Korthorst explains how PDKs can help accelerate the photonic IC design process by offering building blocks such as several types of waveguides, passive devices like splitters, combiners, and filters, along with active devices such as phase shifters, detectors, semiconductor optical amplifiers, and lasers. Siemens EDA's Harry Foster examines IC and ASIC design trends, including... » read more

Week In Review: Design, Low Power
By Jesse Allen - 16 Dec, 2022 - Comments: 0

Power always has been a function of cost. The more power required, the more it costs to run a device, both in dollars and carbon footprint. This makes the breakthrough in fusion ignition at Lawrence Livermore National Laboratory all the more noteworthy, and one that could have significant implications for the future of computing, from data centers to rechargeable batteries in automobiles, robot... » read more

Blog Review: Dec. 14
By Jesse Allen - 14 Dec, 2022 - Comments: 0

Siemens EDA's Harry Foster checks out design and verification language adoption trends in FPGA projects, including testbench methodologies and assertion languages. Cadence's Veena Parthan finds that giving electric vehicle batteries a second life as energy storage devices can extend their useful life by 5 to 8 years, but a lack of standardization in EV batteries poses challenges. Synopsys... » read more

Week In Review: Design, Low Power
By Jesse Allen - 09 Dec, 2022 - Comments: 0

Tools, IP, design Codasip launched a new organization within the company to support the development and commercialization of technical innovations in key applications including security, functional safety, and AI/ML. "As semiconductor scaling is showing its limits, there is an obvious need for new ways of thinking. We will be working with universities, research institutes and strategic partner... » read more

Blog Review: Dec. 7
By Jesse Allen - 07 Dec, 2022 - Comments: 0

Siemens EDA's Harry Foster looks at the continual maturing of FPGA functional verification processes through increasing adoption of various simulation-based and formal verification techniques. Synopsys' Stewart Williams introduces the Scalable Open Architecture for Embedded Edge (SOAFEE) project and how it can make automotive software development, testing, virtual prototyping, and validation... » read more

Week In Review: Design, Low Power
By Marie C. Baca - 02 Dec, 2022 - Comments: 0

Tools and IP Renesas released a family of configurable clock generators with an internal crystal oscillator for PCIe and networking applications in high-end computing, wired infrastructure and data center equipment. “Timing needs can vary greatly between different applications and equipment, and often change during a product design cycle,” said Zaher Baidas, Vice President of the Timing Pr... » read more

Blog Review: Nov. 30
By Jesse Allen - 30 Nov, 2022 - Comments: 0

Cadence's Sangeeta Soni explores how the configuration space for CXL 1.1 and CXL 2.0 varies and discusses newly introduced registers for the CXL-compliant devices and how they are discovered during the CXL enumeration flow. Siemens EDA's Harry Foster continues examining trends in FPGA verification effort by looking at where both design and verification engineers spend their time. Synopsys... » read more

Improving Concurrent Chip Design, Manufacturing, And Test Flows
By Ann Mutschler - 28 Nov, 2022 - Comments: 0

Semiconductor design, manufacturing, and test are becoming much more tightly integrated as the chip industry seeks to optimize designs using fewer engineers, setting the stage for greater efficiencies and potentially lower chip costs without just relying on economies of scale. The glue between these various processes is data, and the chip industry is working to weave together various steps t... » read more

Radiation Tolerance Is Not Just For Rocket Scientists
By Synopsys - 23 Nov, 2022 - Comments: 0

As technology scales, soft errors from particle radiation are becoming increasingly concerning for in-field reliability. These radiation effects are called Single Event Upsets (SEU) and the frequency of the failures due to SEUs is known as the Soft Error Rate (SER). Soft errors are failures due to external sources. By contrast, hard errors refer to actual process manufacturing defects or electr... » read more

An Organic Package Designer’s Guide To Transitioning To FOWLP And 2.5D Design
By Siemens EDA - 23 Nov, 2022 - Comments: 0

The IC packaging design tool set has matured to the point where it can address not only classic plastic, organic and ceramic packaging substrates but can also address silicon substrates driven by interposer and chiplet designs. In most cases system and packaging teams do not have to abandon their existing tool set to support these designs. In fact, the packaging design tool set can offer additi... » read more

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