category: Architectures

category: IoT, Security & Automotive

HyperRec: Efficient Recommender Systems with Hyperdimensional Computing
By Technical Paper Link - 12 May, 2021 - Comments: 0

A group of researchers are taking a different approach to AI. The University of California at San Diego, the University of California at Irvine, San Diego State University and DGIST recently presented a paper on a new hardware algorithm based on hyperdimensional (HD) computing, which is a brain-inspired computing model. The new algorithm, called HyperRec, uses data that is modeled with bina... » read more

Enabling Efficient and Flexible FPGA Virtualization for Deep Learning in the Cloud
By Technical Paper Link - 06 Mar, 2021 - Comments: 0

SOURCE: Shulin Zeng, Guohao Dai, Hanbo Sun, Kai Zhong, Guangjun Ge, Kaiyuan Guo, Yu Wang, Huazhong Yang(Tsinghua University, Beijing, China).  Published on arXiv:2003.12101 [cs.DC])   ABSTRACT: "FPGAs have shown great potential in providing low-latency and energy-efficient solutions for deep neural network (DNN) inference applications. Currently, the majority of FPGA-based DNN accel... » read more

Plasticine: A Reconfigurable Architecture For Parallel Patterns (Stanford)
By Technical Paper Link - 16 Jan, 2020 - Comments: 0

Source: Stanford University Stanford University has been developing Plasticine, which allows parallel patterns to be reconfigured. "ABSTRACT Reconfigurable architectures have gained popularity in recent years as they allow the design of energy-efficient accelerators. Fine-grain fabrics (e.g. FPGAs) have traditionally suffered from performance and power inefficiencies due to bit-level ... » read more

Understanding the Interactions of Workloads and DRAM Types: A Comprehensive Experimental Study
By Technical Paper Link - 31 Dec, 2019 - Comments: 0

Abstract "It has become increasingly difficult to understand the complex interaction between modern applications and main memory, composed of DRAM chips. Manufacturers are now selling and proposing many different types of DRAM, with each DRAM type catering to different needs (e.g., high throughput, low power, high memory density). At the same time, the memory access patterns of prevalent and... » read more

Silicon CMOS Architecture For A Spin-based Quantum Computer
By Technical Paper Link - 24 Jan, 2018 - Comments: 1

Source: UNSW Sydney Authors: M. Veldhorst (1,2),  H.G.J. Eenink (2,3) , C.H. Yang (2), and A.S. Dzurak (2) 1 Qutech, TU Delft, The Netherlands 2 Centre for Quantum Computation and Communication Technology, School of Electrical Engineering and Telecommunications,UNSW, Sydney, Australia 3 NanoElectronics Group, MESA+ Institute for Nanotechnology,University of Twente, The Netherlands Te... » read more

Using Run-Time Reverse-Engineering to Optimize DRAM Refresh
By Technical Paper Link - 31 Dec, 2017 - Comments: 0

Abstract: "The overhead of DRAM refresh is increasing with each density generation. To help offset some of this overhead, JEDEC designed the modern Auto-Refresh command with a highly optimized architecture internal to the DRAM---an architecture that violates the timing rules external controllers must observe and obey during normal operation. Numerous refresh-reduction schemes manually refresh ... » read more

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