category: Transistors

category: IoT, Security & Automotive

Improving the Electrical Performance and Low-Frequency Noise Properties of p-Type TFET
By Technical Paper Link - 08 Nov, 2022 - Comments: 0

A new technical paper titled "Effect of high-pressure D2 and H2 annealing on LFN properties in FD-SOI pTFET" was published by researchers at Chungnam National University and Korea Polytechnic College. "This study investigated the effects of high-pressure deuterium (D2) annealing and hydrogen (H2) annealing on the electrical performance and low-frequency noise (LFN) of a fully depleted silic... » read more

Novel Multi-Independent Gate-Controlled FinFET Technology
By Technical Paper Link - 08 Nov, 2022 - Comments: 0

A new technical paper titled "Characteristics of a Novel FinFET with Multi-Enhanced Operation Gates (MEOG FinFET)" was published by researchers at Changzhou University. Abstract: "This study illustrates a type of novel device. Integrating fin field-effect transistors (FinFETs) with current silicon-on-insulator (SOI) wafers provides an excellent platform to fabricate advanced specific device... » read more

Red MicroLEDs Three Orders of Magnitude Smaller in Surface Area
By Technical Paper Link - 08 Nov, 2022 - Comments: 0

A technical paper titled "N-polar InGaN/GaN nanowires: overcoming the efficiency cliff of red-emitting micro-LEDs" was published by researchers at University of Michigan. The researchers created "red-microLEDs that are nearly three orders of magnitude smaller in surface area than previously reported devices while exhibiting external quantum efficiency of ~1.2%," according to the University o... » read more

L-FinFET Neuron For A Highly Scalable Capacitive Neural Network (KAIST)
By Technical Paper Link - 31 Oct, 2022 - Comments: 0

A new technical paper titled "An Artificial Neuron with a Leaky Fin-Shaped Field-Effect Transistor for a Highly Scalable Capacitive Neural Network" was published by researchers at KAIST (Korea Advanced Institute of Science and Technology). “In commercialized flash memory, tunnelling oxide prevents the trapped charges from escaping for better memory ability. In our proposed FinFET neuron, t... » read more

Full Wafer Integration of Aggressively Scaled 2D-Based Logic Circuits (Imec)
By Technical Paper Link - 28 Oct, 2022 - Comments: 0

A technical paper titled "Challenges of Wafer-Scale Integration of 2D Semiconductors for High-Performance Transistor Circuits" was published by researchers at Imec. "The introduction of highly scaled 2D-based circuits for high-performance logic applications in production is projected to be implemented after the Si-sheet-based CFET devices. Here, a view on the requirements needed for full waf... » read more

Bottoms Up: Arranging Nanoscale Particles On A Silicon Chip (Or Other Materials) Without Damage
By Technical Paper Link - 26 Oct, 2022 - Comments: 0

A new research paper titled "Nanoparticle contact printing with interfacial engineering for deterministic integration into functional structures" was just published by researchers at MIT. “This approach allows you, through engineering of forces, to place the nanoparticles, despite their very small size, in deterministic arrangements with single-particle resolution and on diverse surfaces, ... » read more

Simulating the Groundstate and Dynamics of Quantum Critical Systems
By Technical Paper Link - 18 Oct, 2022 - Comments: 0

A new technical paper titled "Simulating groundstate and dynamical quantum phase transitions on a superconducting quantum computer" was published by researchers at London Centre for Nanotechnology, University College London, University of Massachusetts, and Google Quantum AI. Abstract (partial) "The phenomena of quantum criticality underlie many novel collective phenomena found in condensed... » read more

Hardware Platform Based on 2D Memtransistors
By Technical Paper Link - 15 Oct, 2022 - Comments: 0

A new technical paper titled "Hardware implementation of Bayesian network based on two-dimensional memtransistors" from researchers at Penn State University. "In this work, we demonstrate hardware implementation of a BN [Bayesian networks] using a monolithic memtransistor technology based on two-dimensional (2D) semiconductors such as monolayer MoS2. First, we experimentally demonstrate a lo... » read more

Thermal Scanning Probe Lithography
By Technical Paper Link - 13 Oct, 2022 - Comments: 0

A new technical paper titled "Edge-Contact MoS2 Transistors Fabricated Using Thermal Scanning Probe Lithography" was published by researchers at École Polytechnique Fédérale de Lausanne (EPFL). "Thermal scanning probe lithography (t-SPL) is a gentle alternative to the typically used electron beam lithography to fabricate these devices avoiding the use of electrons, which are well known to... » read more

Highly Dense And Vertically Aligned Sub-5 nm Silicon Nanowires
By Technical Paper Link - 11 Oct, 2022 - Comments: 0

A new technical paper titled "Catalyst-free synthesis of sub-5 nm silicon nanowire arrays with massive lattice contraction and wide bandgap" was published by researchers at Northeastern University, Korea Institute of Science and Technology, Gyeongsang National University and others. "Here, we prepare highly dense and vertically aligned sub-5 nm silicon nanowires with length/diameter aspect r... » read more

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