category: Transistors

category: IoT, Security & Automotive

Hardware Encryption: Ultra-compact Active Interconnect Based on FeFET
By Technical Paper Link - 02 May, 2022 - Comments: 0

New technical paper "Hardware functional obfuscation with ferroelectric active interconnects" from researchers at Penn State, Rochester Institute of Technology, GlobalFoundries Fab1, North Dakota State University. Abstract "Existing circuit camouflaging techniques to prevent reverse engineering increase circuit-complexity with significant area, energy, and delay penalty. In this paper, we... » read more

Vertically stacked, low-voltage organic ternary logic circuits including nonvolatile floating-gate memory transistors
By Technical Paper Link - 02 May, 2022 - Comments: 0

Research paper from KAIST and Gachon University. Abstract "Multi-valued logic (MVL) circuits based on heterojunction transistor (HTR) have emerged as an effective strategy for high-density information processing without increasing the circuit complexity. Herein, an organic ternary logic inverter (T-inverter) is demonstrated, where a nonvolatile floating-gate flash memory is employed to ... » read more

Efficacy of Transistor Interleaving in DICE Flip-Flops at a 22 nm FD SOI Technology Node
By Technical Paper Link - 25 Apr, 2022 - Comments: 0

New research paper from University of Saskatchewan, with funding by NSERC and the Cisco University Research Program. Abstract "Fully Depleted Silicon on Insulator (FD SOI) technology nodes provide better resistance to single event upsets than comparable bulk technologies, but upsets are still likely to occur at nano-scale feature sizes, and additional hardening techniques should be explor... » read more

Improved graphene-base heterojunction transistor with different collector semiconductors for high-frequency applications
By Technical Paper Link - 10 Apr, 2022 - Comments: 0

New research paper from TU Dresden & others. Abstract "A new kind of transistor device with a graphene monolayer embedded between two n-typesilicon layers is fabricated and characterized. The device is called graphene-base heterojunction transistor (GBHT). The base-voltage controls the current of the device flowing from the emitter via graphene to the collector. The transit time for e... » read more

NIST Modifies & Improves Technique For Detecting Transistor Defects
By Technical Paper Link - 04 Apr, 2022 - Comments: 0

Abstract "We utilize a frequency-modulated charge pumping methodology to measure quickly and conveniently single “charge per cycle” in highly scaled Si/SiO2 metal–oxide–semiconductor field effect transistors. This is indicative of detection and manipulation of a single interface trap spin species located at the boundary between the SiO2 gate dielectric and Si substrate (almost certainl... » read more

Vertical MoS2 transistors with sub-1-nm gate lengths
By Technical Paper Link - 15 Mar, 2022 - Comments: 0

Abstract "Ultra-scaled transistors are of interest in the development of next-generation electronic devices. Although atomically thin molybdenum disulfide (MoS2) transistors have been reported, the fabrication of devices with gate lengths below 1 nm has been challenging. Here we demonstrate side-wall MoS2 transistors with an atomically thin channel and a physical gate length of sub-1 nm ... » read more

Large-area photonic lift-off process for flexible thin-film transistors
By Technical Paper Link - 15 Mar, 2022 - Comments: 0

Abstract "Fabricating flexible electronics on plastic is often limited by the poor dimensional stability of polymer substrates. To mitigate, glass carriers are used during fabrication, but removing the plastic substrate from a carrier without damaging the electronics remains challenging. Here we utilize a large-area, high-throughput photonic lift-off (PLO) process to rapidly separate polymer f... » read more

NAND and NOR logic-in-memory comprising silicon nanowire feedback field-effect transistors
By Technical Paper Link - 15 Mar, 2022 - Comments: 0

Abstract: "The processing of large amounts of data requires a high energy efficiency and fast processing time for high-performance computing systems. However, conventional von Neumann computing systems have performance limitations because of bottlenecks in data movement between separated processing and memory hierarchy, which causes latency and high power consumption. To overcome this hindra... » read more

Zero-Bias Power-Detector Circuits based on MoS2 Field-Effect Transistors on Wafer-Scale Flexible Substrates
By Technical Paper Link - 08 Mar, 2022 - Comments: 0

Abstract: "We demonstrate the design, fabrication, and characterization of wafer-scale, zero-bias power detectors based on two-dimensional MoS2 field effect transistors (FETs). The MoS2 FETs are fabricated using a wafer-scale process on 8 μm thick polyimide film, which in principle serves as flexible substrate. The performances of two CVD-MoS2 sheets, grown with different processes and showi... » read more

Label-Free C-Reactive Protein Si Nanowire FET Sensor Arrays With Super-Nernstian Back-Gate Operation
By Technical Paper Link - 13 Feb, 2022 - Comments: 0

Abstract: "We present a CMOS-compatible double gate and label-free C-reactive protein (CRP) sensor, based on silicon on insulator (SOI) silicon nanowires arrays. We exploit a reference subtracted detection method and a super-Nernstian internal amplification given by the double gate structure. We overcome the Debye screening of charged CRP proteins in solutions using antibodies fragments as c... » read more

← Older posts Newer posts →

  • Sponsors

About

Navigation

Connect With Us

Copyright ©2013-2025 SMG   |  Terms of Service  |  Privacy Policy