category: Top Stories

category: IoT, Security & Automotive

Cheaper Packaging Options Ahead
By Ed Sperling - 05 Feb, 2018 - Comments: 0

Lower-cost packaging options and interconnects are either under development or just being commercialized, all of which could have a significant impact on the economics of advanced packaging. By far, the most cited reason why companies don't adopt advanced [getkc id="27" kc_name="packaging"] is cost. Currently, silicon [getkc id="204" kc_name="interposers"] add about $30 to the price of a med... » read more

Testing Analog Chips
By Jeff Dorsch - 05 Feb, 2018 - Comments: 0

The world of analog components is broad and diverse, and while testing analog chips may not take as long as running tests on complex SoCs, there are different requirements for analog devices. One type of chip that's seeing more application these days is analog microelectromechanical system devices. Automotive electronics call for a number of [getkc id="37" kc_name="analog"] chips, along with... » read more

Packaging Challenges For 2018
By Mark LaPedus - 08 Jan, 2018 - Comments: 0

The IC packaging market is projected to see steady growth this year, amid ongoing changes in the landscape. The outsourced semiconductor assembly and test ([getkc id="83" kc_name="OSAT"]) industry, which provides third-party packaging and test services, has been consolidating for some time. So while sales rising, the number of companies is falling. In late 2017, for example, [getentity id="2... » read more

Auto Chip Test Issues Grow
By Jeff Dorsch - 08 Jan, 2018 - Comments: 0

By Jeff Dorsch & Ed Sperling Semiconductor suppliers are flocking to the automotive chip market to gain share in fitting out the connected car and the autonomous vehicle. But before those chips are sold to automotive manufacturers and Tier 1 suppliers, they must be tested and certified to meet stringent industry standards. This is no ordinary testing, though. Assisted and autonomous v... » read more

Getting Serious About Chiplets
By Ann Mutschler - 08 Jan, 2018 - Comments: 0

Demand for increasingly complex computation, more features, lower power, and shorter lifecycles are prompting chipmakers to examine how standardized hard IP can be used to quickly assemble systems for specific applications. The idea of using chiplets, with or without a package, has been circulating for at least a half-dozen years, and they can trace their origin back to IBM's packaging schem... » read more

Fan-Outs vs. TSVs
By Jeff Dorsch - 13 Dec, 2017 - Comments: 0

Two years ago, at the annual IMAPS conference on 2.5D and 3D chip packaging, the presentations were dominated by talk of fan-out wafer-level packaging. There was almost no talk of through-silicon vias, which previously had been heralded as vital to 2.5D and 3DIC packaging. Fast forward to this month's 3D Architectures for Heterogeneous Integration and Packaging conference in Burlingame, Cali... » read more

Changes Ahead For Test
By Jeff Dorsch - 11 Dec, 2017 - Comments: 0

Testing microprocessors is becoming more difficult and more time consuming as these devices are designed to take on more complex tasks, such as accelerating artificial intelligence computing, enabling automated driving, and supporting deep neural networks. This is not just limited to microprocessors, either. Graphics processing units are grabbing market share in supercomputing and other area... » read more

Shortages Hit Packaging Biz
By Mark LaPedus - 11 Dec, 2017 - Comments: 1

Rising demand for chips is hitting the IC packaging supply chain, causing shortages of select manufacturing capacity, various package types, leadframes and even some equipment. Spot shortages for some IC packages began showing up earlier this year, but the problem has been growing and spreading since then. Supply imbalances reached a boiling point in the third and fourth quarters of this yea... » read more

3D Neuromorphic Architectures
By Katherine Derbyshire - 11 Dec, 2017 - Comments: 1

Matrix multiplication is a critical operation in conventional neural networks. Each node of the network receives an input signal, multiplies it by some predetermined weight, and passes the result to the next layer of nodes. While the nature of the signal, the method used to determine the weights, and the desired result will all depend on the specific application, the computational task is simpl... » read more

Litho Options For Panel Fan-out
By Mark LaPedus - 06 Nov, 2017 - Comments: 2

Several packaging houses are inching closer to production of panel-level fan-out packaging, a next-generation technology that promises to reduce the cost of today’s fan-out packages. In fact, ASE, Nepes, Samsung and others already have installed the equipment in their panel-level fan-out lines with production slated for 2018 or so. But behind the scenes, panel-level packaging houses contin... » read more

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