2.5D And 3D-IC Latch-Up Prevention


2.5D/3D ICs have evolved into an innovative solution for many design and integration situations, but they present unique verification obstacles that challenge electronic design automation (EDA) tools originally designed for 2D ICs. Automated solutions are needed not only to reduce verification cycles but also to improve the quality and reliability of package designs. Automated verification o... » read more

Radar Wave Propagation Through Materials


This white paper focuses on electromagnetic (EM) wave propagation through materials. For radar systems, this is of interest when radar must pass through walls, or when designing radomes (cover casings for the radar system). In the process of designing a radome, you should always perform full EM simulation. However, the content of this white paper will help you to first estimate whether a radome... » read more

Post-Quantum Cryptography


Quantum computing is increasingly seen as a threat to communications security: rapid progress towards realizing practical quantum computers has drawn attention to the long understood potential of such machines to break fundamentals of contemporary cryptographic infrastructure. While this potential is so far firmly theoretical, the cryptography community is preparing for this possibility by deve... » read more

10X Higher Productivity With VCS Dynamic Test Loading


The verification of a system-on-chip (SoC) is becoming increasingly complex, due to the multitude of functionality being implemented on a single chip. Different verification techniques are required at each level (IP, block, SoC and system) for faster verification closure. A successful verification strategy requires reuse of functional tests, faster test development and faster debug to improve t... » read more

Harness System-Level Data To Optimize Many-Core AI And ML Chips


The novel multicore architectures of SoCs for machine learning (ML) and artificial intelligence (AI) applications are expected to deliver huge improvements in power efficiency. However, chip development teams and the customers for their devices face the growing complexity of hardware-software co-optimization, validation, and debug. In short, these SoCs are increasingly difficult to validate and... » read more

Multi-Layer Deep Data Performance Monitoring And Optimization


Combining functional and parametric monitoring of the real-world behavior of complex SoCs provides a powerful new approach that facilitates performance optimization during development and in the field, improves security and safety, and enables predictive maintenance to prevent field failures. proteanTecs’ Universal Chip Telemetry (UCT) and Siemens’ Tessent Embedded Analytics are complementa... » read more

Characterization Of Micro-Bumps For 3DIC Wafer Acceptance Tests


The strong market needs to embed multiple functionalities from different semiconductor processing technologies into a single system continue to drive demands for more advanced 3DIC packaging technologies. Dimensions of copper pillar micro-bumps are consistently reduced in every new technology node to facilitate the 3D stacking of multiple dies so that overall system performance can be improved.... » read more

Residual Stress With EIGER2 R 500K


Many manufacturing processes leave residual stresses which can affect the performance of manufactured components. Compressive stress can be engineered into a metal coating to resist crack propagation, while tensile stress can be exploited to enhance conductivity in semiconductors. Strained materials exhibit changes in atomic spacing which can be detected by X-ray diffraction (XRD) and related t... » read more

In-Line Airborne Particle Sensing Supports Faster Response To Contamination Excursions


Fine particles (less than 5 micrometers in diameter) do not affect most industrial processes, but they can have a disastrous impact on semiconductor manufacturing. From the earliest days, manufacturing facilities have deployed air filtering and recirculation to remove particles from the cleanroom, but particles may still be generated inside process tools, where they can cause defects and yield ... » read more

The Evolving Landscape Of SoC Vulnerabilities And Analog Threats


SoC integrators know that a software-only chip security plan leaves devices open to attack. The more effective way to thwart hackers is to combat both digital and analog threats by incorporating security-focused hardware modules built into the core machine design. This paper describes sources of vulnerabilities to cyber attacks and what infrastructure is needed to secure against them. The So... » read more

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