category: Whitepapers

category: IoT, Security & Automotive

4 Horsemen Of Wire Harness Manufacturing
By Siemens EDA - 03 Mar, 2021 - Comments: 0

Growing demands for automotive electrical and electronic (E/E) features drive increased complexity in the wiring harnesses that carry power and data signals to components around the vehicle. As a result, the wire harness manufacturing industry is expected to see significant growth, expanding into a 91 billion dollar industry in 2025. However, wire harness manufacturers often operate on small pr... » read more

Achieving Faster Closure With Reduced Setup And Debug Using Advanced RTL Static Signoff Platform
By Synopsys - 03 Mar, 2021 - Comments: 0

Many design houses are continually seeking ways to shorten their effective design cycle to address demanding market requirements, gain a formidable technological advantage, and secure leadership in their respective industries. This pressure can cause designers to get extremely overwhelmed by strict timelines. To meet tight project timelines, design teams often resort to identifying industry-lea... » read more

Surviving The Three Phases Of High Density Advanced Packaging Design
By Siemens EDA - 24 Feb, 2021 - Comments: 0

The growth of High Density Advanced Packages (HDAP) such as FOWLP, CoWoS, and WoW is triggering a convergence of the traditional IC design and IC package-design worlds. To handle these various substrate scenarios, process transformation must occur. This paper discusses the three phases of HDAP design and provides tips on how to survive their challenges. To read more, click here. » read more

Distributed Development Of IP And SoC In Compliance With Automotive ISO 26262
By Synopsys - 24 Feb, 2021 - Comments: 0

Automotive functional safety System-on-Chips (SoCs) for Advanced Driver Assistance Systems (ADAS) contain several complex Intellectual Property (IP) cores. The IP cores are developed as a Safety Element out of Context (SEooC), meaning the context of the end application is not fully known at delivery time. In addition, IP development might be distributed across the globe. To reduce the risk of f... » read more

5G NR Design For eMBB
By Cadence - 24 Feb, 2021 - Comments: 0

This white paper examines the design challenges for eMBB products and provides examples of how these challenges can be overcome using the co-design capabilities in Cadence AWR Design Environment software. Click here to download with registration. » read more

OVP Guide To Using Processor Models
By Imperas - 24 Feb, 2021 - Comments: 0

The OVP simulation technology from Open Virtual Platforms (OVP) and Imperas Software Limited enables very high performance simulation, debug and analysis of virtual platforms containing multiple processor and peripheral models. The OVP technology is extensible, provides the ability to create new models of processors and other platform components by writing C/C++ code that uses application progr... » read more

WLFO For High-Performance Low-Cost Packaging Of RFMEMS-CMOS
By Amkor - 17 Feb, 2021 - Comments: 0

Navigating the trade-offs between performance, size, cost and reliability can be a challenge when considering integrated circuit (IC) packaging and the end-application. The integration of micro-electromechanical systems (MEMS), either monolithic or heterogeneous, introduces yet another level of complexity that has only recently been a major focus of multi-device packaging. Wafer-level fanout (W... » read more

Marangoni Effect-Based Under-Layer For A Dual Damascene Via-First Approach
By Brewer Science - 17 Feb, 2021 - Comments: 0

One of the main challenges of a Dual Damascene (DD) via-first process is the control of the Critical Dimensions (CDs) in the lithography of the trenches. The PhotoResist (PhR) thickness presents variations from the via arrays to the open areas, which cause the variation of CDs: the swing effect. The planarization of a DD via-first process is reported. A dual-layer solution is used to demonstrat... » read more

Evaluation Of The Impact Of Source Drain epi Implementation On Logic Performance Using Combined Process And Circuit Simulation
By Coventor - 17 Feb, 2021 - Comments: 0

In this paper, we explore an end-to-end solution using SEMulator3D to address the need to include process variation effects in circuit simulation. For the first time, we couple SEMulator3D with BSIM compact modeling to evaluate process variation impacts on circuit performance. The process integration goal of the study was to optimize contacts and spacer thickness of advanced-node FinFETs in ter... » read more

Analysis And Development of Safety-Critical Embedded Systems
By Ansys - 13 Feb, 2021 - Comments: 0

Today’s automobiles and airplanes feature more electronic components than ever. Hundreds of connected systems enable safety-critical functions like braking, acceleration, steering, navigation and communication. Ansys has the only comprehensive simulation solution for designing safe, reliable systems — including hardware, electronics and embedded software — for human-controlled and autonom... » read more

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