Nine Effective Features Of NVMe Verification IP For PCIe-Based SSD Storage


Non-Volatile Memory Express (NVMe) is a new software interface optimized for PCIe Solid State Drives (SSD). This paper provides an overview of the NVMe specification and examines some of its key features. We will discuss its pros and cons, compare it to other conventional technologies, and point out key areas to focus on during its verification. You will learn how NVMe Questa Verification IP... » read more

Designing ASIPs With Confidence


Well-designed ASIPs with a strong SDK combine C/C++ programmability with the power and performance of dedicated hardware. Product families based on ASIP platforms are often highly flexible, capable of addressing multiple market segments with the same silicon and handling updates in the field. They lean well towards software-driven verification with few penalties for late product requirement cha... » read more

Multiband Active Antenna Tuner For Cellular IoT Applications


This white paper discusses related design challenges and solutions for developing a multiband active antenna tuner for cellular internet of things (IoT) massive machine-type communications (mMTC) applications. Click here to read more. » read more

A Layered Approach To High Performance Device Virtualization


The complexity and performance requirements of computing systems have been growing and demands are further driven by applications, such as ML and the everything-connected world of IoT with many billions of connected devices. Arm has developed a virtualization and accelerator strategy to address this, which we discuss in this white paper from our Architecture and Technology Group A layered... » read more

Development Of Digital Controlled Technology For High Voltage DC Testing


In recent years, the demand for low power devices has increased due to issues related to global environmental protection. As a result, the demand for high-voltage power devices has also increased. To test such devices, test equipment that can handle high-voltage devices (hereinafter referred to as “test equipment”) is required. In addition, test time must be shortened to reduce manufacturin... » read more

Controlling TC SAW Filter Frequency with Picosecond Ultrasonics


Presented during the poster session at ASMC 2019 PULSE™ technology is a first principles based acoustic metrology technique that is capable of measuring various parameters of interest in semiconductor manufacturing such as multi-layered metal thickness, sound velocity of dielectric films and reflectivity. In this paper, we demonstrate the applications of PULSE technology in the TC-SAW... » read more

Fast Cycle Approximate Simulation Using ARC nSIM NCAM


One of the key factors of successful software (e.g. firmware/application) development is the ability to quickly run and profile software in the absence of target hardware. The earlier in the design process that this is possible, the better, i.e. during the pre-silicon phase. Typically, the pre-silicon phase is dominated by three activities, each with different challenges: Exploring the Ha... » read more

4 Horsemen Of Wire Harness Manufacturing


Growing demands for automotive electrical and electronic (E/E) features drive increased complexity in the wiring harnesses that carry power and data signals to components around the vehicle. As a result, the wire harness manufacturing industry is expected to see significant growth, expanding into a 91 billion dollar industry in 2025. However, wire harness manufacturers often operate on small pr... » read more

Achieving Faster Closure With Reduced Setup And Debug Using Advanced RTL Static Signoff Platform


Many design houses are continually seeking ways to shorten their effective design cycle to address demanding market requirements, gain a formidable technological advantage, and secure leadership in their respective industries. This pressure can cause designers to get extremely overwhelmed by strict timelines. To meet tight project timelines, design teams often resort to identifying industry-lea... » read more

Surviving The Three Phases Of High Density Advanced Packaging Design


The growth of High Density Advanced Packages (HDAP) such as FOWLP, CoWoS, and WoW is triggering a convergence of the traditional IC design and IC package-design worlds. To handle these various substrate scenarios, process transformation must occur. This paper discusses the three phases of HDAP design and provides tips on how to survive their challenges. To read more, click here. » read more

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