Challenges At Advanced Nodes

Semiconductor Engineering sat down to discuss finFETs, 22nm FD-SOI and how the how the market will segment over the next few years with Marie Semeria, CEO of Leti; Patrick Soheili, vice president of product management and corporate development at eSilicon; Paul Boudre, CEO of Soitec; and Subramani Kengeri, vice president of global design solutions at GlobalFoundries. What follows are excerpts of that conversation. To view part one of this discussion, click here.

SE: What’s changed to make FD-SOI more viable now than in the past?

Soheili: The key is whether the number of wafers per month is going to be there. There were a lot of questions about viability. But now that you’ve got two giants committed the story changes.

SE: Leti is talking about FD-SOI as a platform. What does that mean?

Semeria: If you design in FD-SOI, it’s fully compatible with all the functions that you can have in CMOS using the same flow. The substrates can be joined. So there is much flexibility, especially if you are using the back biasing. You can manage different restrictions. You can play with the controls, different voltages, and it will be compatible with different functions and memory. It’s compatible with any system.

SE: How have we done with platforms as an industry, though?

Kengeri: We would all love to have one technology platform that fits all. That doesn’t happen easily. But the point here is what can you keep common for different chips built out of the same design infrastructure—maybe 85% in common. With 22nm FD-SOI, customers can re-use the same IP for a wide range of Products and that is the meaning of platform for us. Then there are modular add-ons to enable high performance or low leakage or RF, which are the different flavors we offer. From an enablement point of view, it’s a platform solution and customers have to see that or there is no value. If there were four independent technologies, GlobalFoundries, the customer and the ecosystem have to invest in each of those, so it gets very expensive. With commonality and modular add-ons, you bring down the overall cost and barrier to entering the market.

SE: How much different is designing for FD-SOI than a standard or LP process?

Kengeri: The fact that is a fully depleted SOI, and not the partially depleted SOI of previous generation, means there is no more stigma attached to it. Initially, customers were concerned about deviating from what they’ve been doing for 30 years, but with FD-SOI, which is similar to Bulk CMOS, there is less concern. The whole ecosystem—EDA tools, methodology, signoff and SPICE, architecture, place and route—is very similar to bulk CMOS. The second thing is back bias. With FD-SOI, back biasing is not mandatory, but if you are interested you can bring in better performance, lower power and software-controlled transistor characteristics.

SE: This is forward and back biasing, right?

Kengeri: Yes. The key thing here is that you can go down to 0.4 volts, you can have RF integrated, and you can get finFET-like performance. If there was no compelling value, no one would be adopting this.

Boudre: We have seen it through the development of this technology with our partners, particularly with ST when they started to look at getting the performance at the device level. They use the same device without too much extra work. It’s plug and play. They use the same design and the same tools. If you have a design that needs to be ported to FD-SOI you do have some work to do. But this is similar to a half node where you have to re-tune the clock of a device and make other adjustments. It’s like moving from 45nm to 32nm, and from 32nm to 28nm. It’s that kind of change.

Soheili: We agree. We’ve done a lot of work on bulk CMOS and some work on both 28nm FD-SOI. In those cases, the porting into FD-SOI has been a lot simpler than we thought. There is a jump in IP readiness, which is a critical piece for deployment and mass production. As far as 28nm in general, there is enough benefit to get from when the technology is used in the right way to allow you to consider the cost of doing so. You’re talking about 30% to 50% reduction of the power of the same circuitry. And this is for designs that live and die on battery life.

Boudre: Samsung is also showing how much time they take to bring out this technology at a different density. It’s less than a year. It is a kind of evolution, not a revolution.

Soheili: We haven’t seen real data from production, but our suspicion is that it’s going to get there faster than you might think for a new node.

Semeria: We view this as an opportunity for IoT and the automotive industry and others. It’s just a design step compared to finFETs. That makes it very attractive for companies that cannot enter the semiconductor market without fully depleted SOI. As soon as they demonstrate a product, they can consider the reuse of design and technology previously developed for bulk. It will enlarge the scope of applications. Our commitment is to anticipate and innovate, so we are pushing today into new technologies. One is 3D. A second is finFETs. And a third is FD-SOI. We see this as a way of address the Internet of Things.

SE: There are two trend lines going on today. One is consolidation across the industry. The second is more choices. How does that math work?

Soheili: And there are shrinking R&D budgets for the companies that remain.

Kengeri: The wafer volume is not coming down. The number of designs may be coming down, but the wafer volume per Design is going up and is expected to grow.

Boudre: At 28nm and 22nm, that’s an important issue. I was reading a paper from one vendor where they said the average consumption for the average GPS is 20 milliwatt range. That vendor’s product was running at about 10 milliwatts, and with FD-SOI they got it down to 1 milliwatt. Your GPS is normally off, because when it’s on your battery consumption increases quickly. In the future you may be able to leave it on, and you’ll see more applications available because they don’t need as much power. What we are bringing is the capability to develop new applications and new uses. It will open many new opportunities for applications that cannot easily move to 10nm or 14nm.

Kengeri: It will enable new markets and applications.

Soheili: If you look at some of the companies buying other companies, the R&D budget is relatively flat. So there is a loss of innovation in the industry as a result. That net loss is going to translate into more consolidation on processes and base technologies and an investment in the diversification of those technologies. In the past, they might have picked several options. Not all of these flavors will survive. Some will be forced rather painfully out of the market. And unless you have some of these key advantages embedded in your technology, you’re not going to make it. The stuff that’s sitting on top of it is getting consolidated, and the stuff on the bottom is going to get consolidated.