Challenges In Powering Electrification With GaN And SiC

The wish list of device properties that designers of power management systems would like to have is lengthy, but no single material is yet sufficient for the full range of power control applications.

For control transistors to handle power surges, breakdown voltages should be at least triple the expected operating voltage — 1.2 kilovolts or more for many electric vehicle applications, and close to 200 volts for data center server racks. To conserve space, the same devices also should be able to tolerate high power density.

Device switching and high carrier mobility help reduce switching losses and improve overall system performance. But for any of these devices, the switching frequency — whatever it is — also needs to be stable and controlled, along with the device’s threshold voltage.

Silicon transistors, particularly insulated gate bipolar transistors (IGBTs), are the incumbent technology in many cases. But silicon IGBTs account for about 20% of the total losses in hybrid EV powertrains[^⁠1], according to Kazuoki Matsugatani, senior director at Denso Corp., in a presentation at this year’s VLSI Technology Symposium.

SiC and GaN are promising alternatives, with much larger band gaps and breakdown voltages, as much as 10 times larger than silicon’s. GaN already is well-established in low voltage applications like portable chargers for consumer electronics. It brings high electron mobility and fast switching. SiC currently is able to scale to higher voltages. In both materials, though, dislocations and other defects limit device performance.

Table 1: Key properties of silicon, SiC, and GaN [^⁠2]

Substrate optimization cuts defects, boosts performance
Both SiC and GaN can be grown directly on silicon, but in both cases lattice mismatch introduces substantial stress. Typically, a series of buffer layers is used to accommodate the mismatch. Inevitably, though, the smaller GaN or SiC lattice pulls on the underlying silicon, warping the wafer shape.

Infineon Technologies found that trapped charges in the buffer layer can degrade on-state resistance, as well.[^⁠3] Growing buffer layers is also time-consuming and expensive. The thicker the layer, the higher the cost.

Efforts to optimize the GaN starting material are ongoing. In an interview before this week’s IEEE Electron Device Meeting (IEDM), Han Wui Then, principal engineer at Intel, described the use of engineered 300mm silicon substrates from Shin-Etsu Handotai for GaN growth. A thin (111)-oriented silicon layer serves as a template layer for GaN growth, with underlying oxide and polysilicon layers. The polysilicon layer is intentionally “trap-rich,” and serves to block charge accumulation at the interfaces. The SOI structure facilitates integration with a variety of base layers, notably (100)-oriented silicon. Then said that with this structure, Intel was able to achieve 4X better substrate resistivity than more conventional GaN-on-silicon schemes.[⁠4]

Alternatively, Atomera uses dopant-level concentrations of oxygen to introduce compliance into the silicon lattice. While silicon-silicon bonds are four-fold coordinated, oxygen-silicon bonds are only two-fold coordinated. Shawn Thomas, Atomera’s head of advanced logic nodes and power development, explained that trace amounts of oxygen introduce some give into the lattice. As a result, the process reduces wafer warpage by about 15%, and should enable thinner buffer layers.

Even better lattice matching is achieved when GaN is grown on sapphire (Al₂O₃). In work presented at IEDM, UCSB professor Umesh Mishra observed that a sapphire substrate reduces the necessary buffer layer thickness by 60% while also improving isolation and thermal conductivity. Renesas Electronics has demonstrated 1.2 kV switches in GaN on sapphire, he said.[⁠5]

Alternative substrates complicate integration with other materials, though. As Intel’s Then pointed out, growing GaN on silicon makes the full 300mm CMOS toolset available. No other platform is as versatile.

Growing SiC on silicon is also possible, but many SiC devices start with freestanding SiC wafers. Hiroshi Kono, manager at Toshiba, explained that the substrate, typically grown by sublimination, tends to have high concentrations of basal plane dislocations. The current-carrying “drift” layer, grown epitaxially, is higher quality, but the basal plane dislocations can induce stacking faults leading to carrier traps and increased device resistance.

Incorporating Schottky barrier diodes in the intervening buffer layers can help minimize this effect. Alternatively, Kono suggested inserting a recombination enhancement layer with a higher dopant concentration between the substrate and the drift layer. Minority carriers originating from the drift layer can be trapped here before reaching the substrate.[^⁠6]

Mixing and matching with layer transfer
While no single material satisfies all aspects of the power device wish list, layer transfer techniques have been used to build devices that draw on the best aspects of multiple materials. For example, most GaN devices depend on a lateral HEMT (high electron mobility transistor) design in which a two-dimensional electron gas (2DEG) forms between the GaN layer and an AlGaN layer. These devices offer fast, efficient switching, but hole mobility is very low. Instead, at last year’s IEDM, Then’s group at Intel combined a GaN-on-silicon MOSHEMT transistor with a transferred silicon PMOS layer. The silicon doping and dopant activation steps take place before the layer is transferred, avoiding damage and thermal budget issues for the underlying GaN. The two layers share the same backend interconnect stack. Similar designs using two-chip implementations suffer from parasitic inductances in the connecting wire bonds.[⁠7]

Fig. 1: Substrate engineering stacks silicon on GaN on silicon. Source: Intel

The thicker buffer layer needed for successful GaN growth also limits it to lateral devices. A group led by Matteo Meneghini, associate professor at the University of Padova, combined lateral GaN HEMTs with vertical SiC transistors. Here, the GaN devices allow fast switching at relatively low voltages, while the SiC devices handle higher voltages. Bonding the GaN and SiC wafers face-to-face minimizes interconnect-related inductances.[2]

GaN and SiC are both relatively new to the semiconductor industry. On one hand, manufacturers are scrambling to build better switches to meet escalating power control requirements. On the other, physicists and materials scientists are still answering fundamental questions about defect and carrier behavior.

Part two of this series will look more closely at specific integration schemes.

References

1. K. Matsugatani, “Mobility Evolution: Electrification and Automation,” 2024 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits), Honolulu, HI, USA, 2024, pp. 1-4, doi: 10.1109/VLSITechnologyandCir46783.2024.10631475.
2. M. Meneghini, et al., “Vertical GaN Devices: Reliability Challenges and Lessons Learned from Si and SiC,” 2024 International Electron Devices Meeting (IEDM), San Francisco, CA, USA, Paper 33.7
3. C. Koller, et al., “Catalyzing Innovation: Bridging System Efficiency to Fundamental Device Physics,” 2024 International Electron Devices Meeting (IEDM), San Francisco, CA, USA, Paper 40.8