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GaN ICs Wanted for Power, EV Markets

For electric vehicles and power devices, device makers are working their way to GaN integrated circuits.


Circuits built with discrete GaN components may get the job done, but fully integrated GaN circuits remain the ultimate goal because they would offer many of the same advantages as integrated silicon circuits.

These benefits include lower cost as the circuit footprint is scaled, and reduced parasitic resistance and capacitance with shorter interconnect runs. In addition, improved device performance allows GaN logic to address more circuit functions — integrating complete systems on a single wafer and enabling the same familiar economies of scale that other semiconductor markets enjoy.

GaN’s large 3.4 eV band gap gives it a higher breakdown voltage than silicon, with low switching and conduction losses. High power applications like electric vehicles need sophisticated power management circuits, which are not yet implemented in GaN. But the material also is well-suited to several low power applications. That accounts for GaN’s mainstream success in LED lighting applications, where it has proven to be a cost-effective material with a manufacturing base that other applications can build on.

Fig. 1: 200V GaN-on-SOI Power IC technology and components. The process features monolithic co-integration of E/D mode HEMTs, Schottky diodes, resistors, capacitors, and includes advanced process modules (deep trench isolation, substrate contact, RDL, etc.)

Fig.1: A GaN-on-SOI platform enables monolithic, integrated devices utilizing deep trench isolation, substrate contacts, and RDL. Source: Imec

Two-dimensional electron (and hole) gases
GaN high electron mobility transistors (HEMTs) differ from silicon MOSFETs in a number of important ways. While carbon in carefully controlled amounts functions as a dopant, charge transport depends primarily on the formation of a two-dimensional “electron gas” (2DEG). Tensile strain at the interface between AlGaN and GaN leads to spontaneous polarization of the interface region, and a discontinuity in the band structure at the interface. Electron mobility is high — on the order of 1,500 cm2/V-s inside the polarized region — but low outside of that region, effectively confining carriers near the interface.

The 2DEG then forms the device channel. It lies between two plates of a capacitor. In depletion mode devices, when the top plate — the gate — is positive, it induces a positive charge on the opposite plate. Negative carriers (electrons) are depleted from the channel and accumulate at the two plates, and conductivity goes down. Depletion mode devices are normally on. Current flows when the gate voltage is less than the threshold voltage.

With enhancement mode devices, in contrast, a positive charge on the gate pulls electrons from p-doped bulk material into the channel. Enhancement mode devices are normally off. When the gate voltage is less than the threshold voltage, no current flows. Especially in power devices, the use of normally on transistors poses safety risks, as current continues to flow even if the control circuit fails. Enhancement mode devices are preferable for this reason.

While the availability of normally on and normally off devices allows the implementation of logic gates, both enhancement and depletion mode devices depend on the flow of electrons. In fact, while enhancement mode devices place a p-GaN layer between the gate and the AlGaN barrier, there is no p-doped material in the current path, and no pn junction in the GaN channel. Nor are there any commercially viable p-channel GaN transistors at this time. The reason is that GaN hole mobility is very low, only 10 to 20 cm2/V-s. At December’s IEEE Electron Device Meeting, Aditya Raj of University of California Santa Barbara (UCSB) explained that several researchers have demonstrated 2D hole gases using AlInGaN-based heterojunctions. Unfortunately, achieving adequate current requires much higher charge densities, in the range of 5 x 1013/cm2. [1]

Without p-GaN devices, CMOS logic is not possible. Instead, Thibault Cosnier, semiconductor process engineer at Imec, explained that GaN circuits depend on resistor-transistor logic (RTL) and direct-coupled FET logic (DCFL). RTL requires a tradeoff between switching time and static power consumption, which is somewhat mitigated by replacing the resistor with a depletion-mode HEMT in a DCFL design. The Imec group reported they were able to produce logic circuits with low leakage and good stability at operating voltages up to 200V. [2]

Circuits built with discrete GaN components perform well today, but fully-integrated GaN circuits would offer desirable cost and performance advantages like scaled silicon CMOS ICs. To that end, manufacturers are pursuing the growth of GaN integrated circuits on silicon wafers.

Engineered wafers for isolation and stacked channels
GaN on silicon wafers not only facilitates integration with silicon transistors, but begins to develop the 200mm process capability the industry needs to support GaN-only circuits.

GaN has different lattice dimensions and thermal expansion characteristics from silicon, which means that combining the two in a wafer that will be flat when cooled requires a series of engineered buffer layers, with thickness controlled to within nanometers, according to Stefaan Decoutere, program director for GaN technology at Imec. The resulting wafer has complex and overlapping lattice strain fields, which is an inescapable aspect of GaN integration. Carrier traps, dislocations, and other defects can accumulate at the many internal interfaces in the resulting structure.

Fig. 1: Cross-sections of high-voltage components showing an enhancement-mode GaN HEMT (a), depletion-mode MIS HEMT (b) and Schottky barrier diode (c). Fabricated on 200mm GaN-on-SOI wafers, the devices operate at 200 V. Source: Imec

Fig. 2: Cross-sections of high-voltage components shows the enhancement-mode GaN HEMT (a), the depletion-mode MIS HEMT (b) and the Schottky barrier diode (c). Stable devices operate at up to 200 V and were built on 200mm GaN-on-SOI wafers. Source: Imec 

Once processes for extremely precise deposition of GaN and related compounds exist, though, engineered superlattices can expand the library of potential device structures. Just as silicon IC manufacturers are investigating stacked nanosheet designs to increase device current, stacked channels designs may help p-GaN devices to achieve adequate currents. The UCSB group reported promising results from a GaN PFET with seven parallel channels, based on a magnesium-doped GaN/AlGaN superlattice.

While integrating multiple GaN devices on a single wafer reduces interconnect parasitics, it’s important to remember that silicon in particular is a conductive substrate. GaN integration increases the potential for interaction and crosstalk between adjacent devices. Good electrical isolation is especially important when high current and low current elements are fabricated on the same substrate. Gang Lyu and colleagues at Hong Kong University of Science and Technology proposed an engineered substrate with highly doped p+ silicon on top of n-doped silicon, followed by the GaN buffer structure. This design places p-n diodes perpendicular to the GaN device layer, which is broken into islands by a deep trench isolation region. The p+ islands allow a local source-to-silicon connection for each GaN transistor, with a backside contact tied to the bus voltage, while the p-n junctions isolate the transistors from interference. [3]

Managing breakdown for a reliable future
Though GaN ICs are a long way from commercialization, some of the issues affecting circuit performance and reliability are becoming clear. For instance, because power devices must manage larger electric fields than logic devices, they are more vulnerable to field-induced failures of various kinds, as Dong Seup Lee, GaN power process integration engineer at Texas Instruments, explained at IEDM. GaN has a high density of surface states because it lacks a high-quality native oxide. He adds that high electric fields near the gate and other metal interfaces can drive electrons into these states. Trapped electrons at the GaN surface are then unable to carry channel current, the depletion width changes, and resistance rises — which may ultimately cause device failure.

Furthermore, the GaN itself can break down. GaN is a polar material. A high electric field induces lattice strain, ultimately leading to defect formation and a path for current leakage. Lee warned device designers of the potential for breakdown due to current concentrations at the edges of the gate and near the source electrodes. In off-state devices, where a large electric field may be present but current is not flowing, researchers at Japan’s National Institute of Advanced Industrial Science and Technology observed sudden and destructive breakdown events similar to dielectric breakdown. To prevent breakdown events, they proposed integrating the SiC diodes into the device substrate to create an alternative current path for excess accumulated charge. [4]

The transition from individual GaN devices to integrated GaN circuits, and from laboratory proofs of concept to commercial applications, inevitably bring reliability and operating envelope questions to the forefront. Researchers and engineers are working through GaN’s unique issues, and the strong pull from EV and power device markets should assure manufacturable solutions.


[1] A. Raj et al., “GaN/AlGaN superlattice based E-mode p-channel MES-FinFET with regrown contacts and >50 mA/mm on-current,” 2021 IEEE International Electron Devices Meeting (IEDM), 2021, pp. 5.4.1-5.4.4, doi: 10.1109/IEDM19574.2021.9720496.
[2] T. Cosnier et al., “200 V GaN-on-SOI Smart Power Platform for Monolithic GaN Power ICs,” 2021 IEEE International Electron Devices Meeting (IEDM), 2021, pp. 5.1.1-5.1.4, doi: 10.1109/IEDM19574.2021.9720591.
[3] G. Lyu et al., “A GaN Power Integration Platform Based on Engineered Bulk Si Substrate with Eliminated Crosstalk between High-Side and Low-Side HEMTs,” 2021 IEEE International Electron Devices Meeting (IEDM), 2021, pp. 5.2.1-5.2.4, doi: 10.1109/IEDM19574.2021.9720505.
[4] A. Nakajima, H. Hirai, Y. Miura and S. Harada, “1.2 kV GaN/SiC-based Hybrid High Electron Mobility Transistor with Non-destructive Breakdown,” 2021 IEEE International Electron Devices Meeting (IEDM), 2021, pp. 36.5.1-36.5.4, doi: 10.1109/IEDM19574.2021.9720673.

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