HBM roadmap from KAIST; RISC-V base station-on-chip; fully automated processor design; analysis of LLMs on HDL-based communication protocol generation; NIST’s HW security constructs; PCM for in-memory computing; vertically stacked ZnO/Te CFETs; lifetime predictions of power devices.
New technical papers recently added to Semiconductor Engineering’s library:
| Name of Paper | Research Organization |
|---|---|
| HBM Roadmap: Overview of Next Generation HBM Architectures | KAIST TERALAB |
| QiMeng: Fully Automated Hardware and Software Design for Processor Chip | Chinese Academy of Sciences |
| Towards a Base-Station-on-Chip: RISC-V Hardware Acceleration for wireless communication | TU Dresden and CeTI |
| ProtocolLLM: RTL Benchmark for SystemVerilog Generation of Communication Protocols | University of Illinois Urbana Champaign and CISPA Helmholtz Center for Information Security |
| Metrics and Methodology for Hardware Security Constructs | NIST |
| Phase-Change Memory for In-Memory Computing | IBM Research-Europe |
| Demonstration of Vertically Stacked ZnO/Te Complementary Field-Effect Transistor | POSTECH and Mokpo National University |
| Impact of Parameter Uncertainties on Power Electronic Device Lifetime Predictions | TU Delft |
Find more semiconductor research papers here.
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