Chip Industry Technical Paper Roundup: Oct. 22

GPU energy; chiplets thermal modeling; ferroelectric thin-film transistors; BEOL-compatible 3D logic; fingerprinting advanced IC packages; signal processing for radar; review of image sensors and photodetectors; semiconductor-free logic gates.

popularity

New technical papers recently added to Semiconductor Engineering’s library:

Technical Paper Research Organizations
MFIT: Multi-Fidelity Thermal Modeling for 2.5D and 3D Multi-Chiplet Architectures University of Wisconsin–Madison, Washington State University, and University of Ulsan
Online Energy Optimization in GPUs: A Multi-Armed Bandit Approach Illinois Institute of Technology, Argonne National Lab and Emory University
An efficient device model for ferroelectric thin-film transistors University of Florida
Omni 3D: BEOL-Compatible 3D Logic with Omnipresent Power, Signal, and Clock Stanford University, Intel Corporation, and Carnegie Mellon University
Fault-marking: defect-pattern leveraged inherent fingerprinting of advanced IC package with thermoreflectance imaging University of Florida and University of Cincinnati
Signal processing architecture for a trustworthy 77GHz MIMO Radar Fraunhofer FHR, Ruhr University Bochum, and Wavesense Dresden GmbH
Image Sensors and Photodetectors Based on Low-Carbon Footprint Solution-Processed Semiconductors Cardiff University
Semiconductor-free, monolithically 3D-printed logic gates and resettable fuses MIT

 

More Reading
Chip Industry Week In Review
AI CPU chiplet platform; Intel-AMD pact; GDDR7 DRAM; AI-RFIC funding; CHIPS Act awards; NoC tiling; thermal modeling on chiplets; $900M nuclear tech and more.

Technical Paper Library home



Leave a Reply


(Note: This name will be displayed publicly)