Chiplets Add New Power Issues

Delivering and managing power are becoming key challenges in the rollout of chiplets, adding significantly to design complexity and forcing chipmakers to weigh tradeoffs that can have a big impact on the performance, reliability, and the overall cost of semiconductors.

Power is a concern for every chip and chiplet design, even if the specifics differ based on the application. Systems vendors and leading-edge chipmakers already are using chiplets to improve performance and power efficiency, and the automotive industry is eyeing them as a way of managing different options for consumers. But while most power-related issues are well understood in a monolithic SoC, accounting for all of the possible interactions in a heterogeneous assembly of chiplets elevates those issues to a whole new level.

“With so many people experimenting and using AI, they are able to do more sophisticated things, and that means you need more power,” said Steven Woo, fellow and distinguished inventor at Rambus. “In a lot of ways, these AI architectures are becoming more power-efficient. It’s just that you’re still getting dwarfed by the increase in the amount of compute you want to do for more advanced AI, so you can’t keep up with the demand. You’re making things more power-efficient, but it’s not enough. You have to find ways to get more power. The models are getting bigger and more accurate. The calculations are more complex, and the hardware is getting more sophisticated. But a lot of it comes down to how to power all of this stuff, and then how to cool it.”

These problems become proportionately more challenging as transistor density increases. What used to fit into a reticle-sized planar SoC now is spilling out into an assortment of chiplets, due to the inability of SRAM to scale to the latest nodes and the increased use of specialized processing elements. The resulting disaggregation of the SoC, and re-aggregation into a heterogeneous assembly of dense chiplets, has opened the door to significantly higher performance. But it also has increased the total power demand for these devices.

“We are already dealing with high power levels of several hundred watts per SoC, and this is significantly amplified by the dense stacking of SoCs in chiplet systems,” noted Andy Heinig, head of Efficient Electronics in Fraunhofer IIS’ Engineering of Adaptive Systems Division. “This power supply must be maintained at even lower supply voltages, meaning the absolute deviation is becoming smaller and smaller. At the same time, it is becoming increasingly difficult in chiplet systems to implement appropriate stabilization techniques, such as capacitors. It is also currently very complicated to set up a unified power simulation or verification, as the interface between the chip and the package is not sufficiently standardized. For example, there are no uniform requirements for describing the currents or loads.”

To make room for all of these compute elements, chipmakers are vertically stacking an increasing amount of both memory and logic. Today, most of these designs involve some type of interposer, but that could change over the next few years as chipmakers focus on better power efficiency.

“In 2.xD systems, high density die-to-die interfaces such as UCIe drive up package layer counts or the need for interposers,” explained Javier DeLaCruz, fellow and senior director of system integration and development at Arm. “This makes the capacitance and voltage regulation on the package ball-side or the PCB less effective, which then drives the need for integration of these elements in the interposer or package substrate. We’ve seen this driving a landscape for more advanced packaging technologies.”

One of the issues with those packages is their size. “The larger the substrate, the stiffer they need to be, which generally means a thicker core layer in a build-up substrate,” DeLaCruz said. “This thicker core layer amplifies the challenge in getting adequate power delivery through package due to the reduced PTH (plated through-hole) via density and higher resultant inductance.”

3D-ICs solve some of those issues with thinner substrates and metal layers. But higher current, along with more voltage domains per unit, can result in power integrity problems and an increase in parasitics.

Stacking up power problems
Most power-related issues are well understood and documented, but in heterogeneous assemblies of chiplets they can interact in unique ways. The greater the number of chiplets, the thinner the materials and dielectrics, and the more compute-intensive the workload, the bigger the impact on power. It’s more difficult to get power to where it’s needed, data paths can close up due to accelerated aging effects caused by inadequate thermal dissipation, and workload-specific thermal gradients can impact both performance and power consumption in unexpected ways.

One effect can have a big impact on another, something that is particularly challenging to keep track of and mitigate in a 3D-IC. “Electromigration is not fundamentally different than on a single chip,” said Marc Swinnen, director of product marketing at Ansys. “It’s just a bigger problem. But it’s mainly the voltage drop, because the power networks are not independent. It’s not like signal wires that are point-to-point. A power mesh is a complete mesh over the entire chip. Then, the other chip has a mesh, the interposer has a mesh, and all those meshes are connected at many hundreds or thousands of points. You can’t analyze one in isolation, another in isolation, and just add them up. It doesn’t work that way. Meshes are very complicated because there are so many points that connect. A signal point is always from one driver to many loads, but power be from many drivers to many loads, and it’s all meshed together. This means the only way you can get the voltage drop accurately is to co-simulate the entire grid of all the chips, the interposer, and the package together to get it done. You can do that, but it takes forever and a huge amount of memory, etc. The better way to go, when you have a dozen chips and all that on the 3D-IC is to use reduced order models.”

Commercial tools are available that look at the chip, do the analysis of the power grid, then produce a chip power model (CPM) that captures what is needed about the behavior and the power grid. “You can have multiple CPMs,” Swinnen said. “You have one for each chip, one for the interposer, one for the package, then you can simulate those altogether as a co-simulation of the package, the interposer and the chips. That’s the hard part about power integrity. It requires co-simulation. You can’t partition, divide and conquer. It doesn’t work that that way.”

New challenges spur new approaches
Designing the power delivery network in a heterogeneous assembly of chiplets is significantly more complex than for a single SoC. The problem on a single chip is largely a real-estate problem, with shrinking nodes forcing increased wire density. This is the main reason for backside power delivery. With chiplets, the bumps and through-silicon vias that need to be connected and perfectly aligned can be daunting.

“The number of bumps that you have to connect together to die directly impacts the power delivery, and the number of bumps required to connect up the power and ground has a direct impact on the maximum temperature of the die,” said Keith Lanier, technical product management director at Synopsys. “It’s about the number of bumps, the size of the bumps, the spacing of the bumps that really have an impact whether you can connect everything up from a power standpoint, and whether you can meet the thermal requirements for that for each die.”

This becomes more difficult as more compute elements are added into a design. “In the future, as things get more and more complex, it’s going to be increasingly more difficult to do that manually, as in running multiple different combinations of, ‘Let’s try what-if analysis. Let me try this space and let me try that.’ When you start to get many more things that interact with each other in terms of being able to analyze them, that’s when it’s really difficult for a human to do it alone without the aid of some sort of artificial intelligence or machine learning. You need to be able to look at the data from the previous designs, look at the data for a large number of runs of analysis. That’s another challenge that you have these days that you wouldn’t have had to think about in the past.”

Others agree. “In SoC design, you just had one package, and that package was dedicated to that SoC, so it was a simple system,” said Rajat Chaudhry, product management group director for Voltus at Cadence. “For one SoC, the power is provided through the package, and it could be a wire-bond or a flip-chip package. Now, in the chiplet system, you have multiple kinds of packaging, so the thought process has to be from the perspective of the complexity of the power delivery being much higher. It could be through an interposer, so now you have to start taking that interposer into account. Or it could be in true stacked 3D-IC. It could even be through different die. You have to take that into account. So one of the biggest considerations is that early planning becomes very critical. In the older style of design, you knew you had a package that you could start designing with, assuming you’re going to get a certain clean supply at the power pins of your design and then start designing. Now, you have multiple chiplets, and you have to really set up that early model for the whole system.”

Ideally, that model allows for what-if kinds of tradeoffs. “What kind of technology or multi-die packaging style works that can satisfy the constraints of what you’re trying to do? That’s one of the biggest changes,” Chaudhry said. “One of the most important things now is to try to make sure early on, ‘Are you way off? Or are you in the ballpark? Can you really make this system work from a power integrity perspective?’ From a methodology perspective, you need early planning tools, where you can specify it very simply, and mock-up something fast and do an optimization loop through that. You can understand how many micro-bumps you need, or how many through-silicon vias you need if you’re going through the interposer.”

Tradeoffs become essential with this level of complexity. “You need a methodology where early on you can mock something up that is reasonably realistic,” he said. “Then you can do your design exploration, and when you pick something, determine whether it meets your constraints. Then, as you mature in the design process, you want to start thinking about doing a more detailed, more refined analysis of each individual chiplet. When you are designing an individual chiplet, previously we had a simple package, and we knew how to model that. Now there are going to be different impacts. Now, the interposer, the other chiplets, their power supply, noise, everything is going to impact this single chiplet, so as you go through the maturity aspect of the design, you can then start bringing in the impact of the other chiplets onto a single chiplet,” Chaudhry continued.

Power modeling
Modeling the entire chiplet flat also becomes challenging because the elements that need to be modeled become very big. Therefore, a hierarchical modeling capability might be necessary to start building models of the remaining chiplets. “You design one chiplet, then you can have a bottom up and top-down approach. You can have a top down where you see at the board level, at the boundaries of the chiplet, what voltage you’re seeing from the top level. Then you can divide the problem and model the single chiplet in much more detail and take the boundary voltages from a higher level simulation, model that, and do the analysis. This means a chiplet designer would do their analysis with the boundary values from a system level perspective,” he said.

So what’s changed from a power perpective? “For 20 or 30 years, people have known what to do,” noted Subramanian Lalgudi, product specialist at Siemens EDA. “There is a chip, there is a package, there is a board. There are different resonances coming out of different things. The chip provides that decoupling capacitance along with package inductance. The package is mostly inductive. From a chip point of view, it causes a resonance. The peak of that resonance is what people want to reduce. There is also a resonance between package capacitance and board inductance, and people who design for power integrity must contend with decoupling capacitors that are shunting to the ground and will be designed for the power planes on the package, and for the board all the way to the regulator.”

This approach works at a fundamental level, but it begins to break down in complex designs where the integrity of that power delivery might be affected by multiple chiplets. “Each of those circuits that you lump in are, in fact, a distributed big structure itself,” Lalgudi said. “This is okay as a rule of thumb, but for finer things, people have to model a distributed space, not just a lump. And unlike signal integrity, there is no real standard in power integrity. We know what the inputs have to look like, what the outputs have to look like. Everybody talks about interoperability. Once you have a standard, everybody adheres to what input, what output will work. You don’t need to know anything beyond what happens inside that transmitting medium. As long as a transmitter can deliver, and meet that spec, you’re through.”

Power integrity
However, with power integrity, there is no clear standard approach. “With the signal integrity process, all you have to verify is the transmitter on the receiver and the interconnection between them,” Lalgudi explained. “You don’t need to worry about what happens in the rest of the chiplet, what happens to the power distribution network, what happens in the package. As long as interconnects go to the package and come back, you need to model that. I call that a local simulation, meaning I don’t need to worry about whether I’m communicating between one processor to HBM or processor-to-processor. I only worry about those two things. I only look at that basic thing and look at my interoperability, look at my signal. But in power integrity, I need to be solving the global problem. I need to be modeling the entirety, and that increases the complexity in terms of memory, runtime, and what I can simulate.”

Chiplets add a new wrinkle to power integrity. “Normally when you’re looking at power, you’re looking at high frequency power noise,” said Ansys’ Swinnen. “As the switching on the transistors pulls on the power, you get a high frequency ripple on the power, also called power noise. That’s voltage drop, essentially. And when the ripple is maximum, that’s your maximum voltage drop. But that’s all assuming high frequency, so it’s like a transistor speed of switching. You can build a model that’s optimized for that. But there’s also low frequency power noise. We’re not talking about gigahertz or hundreds of megahertz. We’re talking like 100 hertz, where the power fluctuates from one side to another because of resonance effects between the different systems. This block switches on, that one switches on, this one switches on, that one switches, and you get this sloshing of the power between different elements. You don’t see that on a monolithic chip because it’s all too small and it’s all tight. But on a distributed, disaggregated system, you get these power resonance effects, and you get low frequency power noise, as well. In fact, the high frequency model you build is often not suitable for doing low frequency analysis, and vice versa. So at some point you also want to build a low frequency model to manage low frequency power noise.”

This impacts the interconnect between chiplets, as well. “A key objective of SiP architects is to move data between chiplets in the most power efficient manner, which requires turning interfaces on quickly to transfer data, and then turning them off again,” said Kevin Donnelly, vice president strategic marketing at Eliyan. “Chiplet architects and designers need to understand that turning interfaces on and off generates large spikes of current in short timeframes, and careful power integrity analysis is required to ensure the dI/dt transitions do not impact data transfer quality.”

Conclusion
Planning for power-related effects in chiplet-based designs is far more difficult than with a planar SoC, and it needs to happen at the very beginning of the design process.

“A classic approach with separate simulations faces the problem that the potential positive and stabilizing capacitive effects at each level must be well modeled,” said Fraunhofer’s Heinig, noting this requires either a precise specification of the chip-package interface or co-simulation. “The percentage of capacitances per chip must be reduced due to the lower packaging density, which involves a very precisely designed power mesh. This works best with a comprehensive simulation of the power grids in both the package and the chip.”

Or put differently, it requires a more extensive system-level approach. “The design of a chiplet cannot be done in the isolation of the type of packaging and PCB solution that will be required for its integration,” said Arm’s DeLaCruz. “This is especially true given that these chiplet systems will trend toward having at least one chiplet in an emerging node as the power density and resulting complexity have been increasing with each node shrink. Chiplet designers need to have representative systems considered, or even measured, to adequately provide the integration guidance needed for other parties using the chiplets.”

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