Confusion Does Not Equal Paralysis

After attending the two biggest semiconductor conferences in the world, along with a long list of notable conferences targeted to a wide variety of technologies and engineering disciplines, it’s clear the industry is racing ahead. But “ahead” is now a relative term.

While Moore’s Law satisfied both economic and technological requirements, it was easy to figure out what “ahead” meant. It was the next process node on the ITRS road map. You could shrink the feature size of components on chips, be guaranteed a payback in terms of area (cost), performance and/or power, and start planning for the next process node.

At 14nm/16nm, with a 20nm back end of line process, the semiconductor industry is standing at a precipice. Unlike the 1 micron wall, this one isn’t a perceived technological impossibility. The technology road map is well-defined and possible. But beyond this point—a 14/16nm BEOL with 10nm finFETs—it becomes an economic impracticality for many companies. FinFETs are more expensive to design, multi-patterning is more expensive and time consuming, high-mobility materials are rarer and harder to work with, and yield for large, complex SoCs is significantly lower.

There are three ways forward. One is to bite the bullet, continue shrinking features and piling more onto a die. Intel and IBM have committed to this at least to 7nm, although even Intel is now looking at eDRAM inside a package rather than on the same die. With 450mm wafer development on hold—maybe permanently—it remains to be seen how well this strategy will work out. At 7nm, even EUV is too large for single patterning.

The second is to invest in older process nodes, and there is plenty of work going on at nodes all the way back to 180nm. New low-power and high-performance versions of process technologies are being added. There are questions about whether FD-SOI can be rolled back, and whether finFETs will be added to older nodes, although the latter appears to be unlikely for the moment.

The third possibility is stacking die, in 2.5D or 3D configurations. This will require some rethinking of cost allocation among corporate departments within chipmakers, but the promise is better yield and quicker turnaround for complex chips, along with lower power and better performance. In fact, stacked die may prove to be the glue between the other two approaches, because it can take advantage of a 7nm processor using high-speed TSVs or photonics to connect to a 180nm sensor and a 14nm 3D NAND structure.

The reality is there are advantages to the first two approaches, depending upon the application, and synergies between both of them in the stacked die world. And for all the fretting about which way to go next, this could turn out to be the smoothest evolution to new semiconductor architectures in the history of technology—and one that opens new opportunities for new participants, enables new architectures, and paves the way for a huge number of new ideas that will make semiconductors and high tech far more pervasive, important—and in some ways potentially far more dangerous—than at anytime in history.