A new technical paper titled “Assessing Design Space for the Device-Circuit Codesign of Nonvolatile Memory-Based Compute-in-Memory Accelerators” was published by TSMC researchers.
Abstract
“Unprecedented penetration of artificial intelligence (AI) algorithms has brought about rapid innovations in electronic hardware, including new memory devices. Nonvolatile memory (NVM) devices offer one such attractive alternative with ∼2× density and data retention after powering off. Compute-in-memory (CIM) architectures further improve energy efficiency by fusing the computation operations with AI model storage. Electronic characteristics of NVM devices, like resistance in the two resistance states, directly affect the circuit designers’ decisions and result in the varying performance of NVM-CIM chips. In this mini review, we assess the bounds on device resistances for accuracy and circuit performance to suggest recommendations to device engineers for frictionless device–circuit–system interactions. Furthermore, we review challenges in reliably programming NVM devices, followed by benchmarking recent NVM-CIM chips. Our literature review and analytical modeling reveal that a high resistance ratio and low variability are favored, and the resistance in a low resistance state is bound by accuracy and circuit performance constraints.”
Find the technical paper here. January 2025.
Lele, Ashwin Sanjay, Bo Zhang, Win-San Khwa, and Meng-Fan Chang. “Assessing Design Space for the Device-Circuit Codesign of Nonvolatile Memory-Based Compute-in-Memory Accelerators.” Nano Letters (2025). DOI: 10.1021/acs.nanolett.4c05299
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