Using an apodized discrete layer thickness design method for notch filters makes error tolerant designs.
Deep Reactive Ion Etch (DRIE) processes used to form through silicon vias (TSVs) achieve high aspect ratios by depositing polymer on the vertical sidewalls of the features. This polymer material must be removed before other materials (including dielectric liner, Cu barrier, and Cu) are deposited in the TSVs. Clean processes adapted from Cu damascene integration flows use a combination of oxygen ash and wet clean to remove the residual photoresist and sidewall polymer to prepare the inside surface of the TSV for subsequent films. In this work, we show the performance of a cleaning process utilizing exclusively wet methods. The removal of both the photoresist and sidewall polymer is accomplished with a combination of soak and high-pressure spray process using an environmentally friendly chemistry. This reduces the total number of process steps, leading to a reduction in overall cost. Previous work has shown that physical analysis, including SEM, EDX, and Auger, as well as electrical testing, are required to determine cleanliness. This study focuses on electrical testing to qualify the performance of the wet-only clean. Electrical testing allows measurement of the aggregate behavior of up to thousands of TSVs. In-line Test (ILT) uses capacitance, leakage, and conductance to determine the performance of the M1 and TSV dielectric liners. Dielectric breakdown voltage measured using a Voltage Ramp Dielectric Breakdown (VRDB) method is used to test the reliability of the TSV dielectric liner. In this work, the cleaning performance was evaluated using two via diameters (2 and 5 microns) and two aspect ratios (10:1 and 20:1).
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