How to work with the new RISC-V debug standard.
Systems with RISC-V cores often include multiple types of other processors and accelerators. Peter Shields, product manager for Tessent at Siemens Digital Industries Software, talks about what’s needed for debug and trace in context, including the need for unobtrusive observation at full speed, what to trace and when to trace it, and how embedded IP can identify to report which branches are taken and which ones aren’t.
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RISC-V Pushes Into The Mainstream
Open-source processor cores are beginning to show up in heterogeneous SoCs and packages.
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