eFPGA Architectural Improvements That Lower Test Cost And Increase Quality

Pipelining key portions of the scan circuitry to increase scan speed.


More than 40 chips have been licensed to use EFLX eFPGA and >20 chips are working in silicon. Big customers like Renesas are planning high volume families of chips using embedded FPGA.

As a result, we have gained extensive experience and knowledge in almost 10 years of doing eFPGA especially in production test for cost reduction and reliability improvement.

eFPGA DFT and MBIST for high quality

Test is a significant fraction of total chip cost.

High volume chip customers first want high quality then want it at the lowest test time (=cost).

Step one is to get high DFT coverage. This is challenging for FPGA as the logic is in a network of interconnect with millions of possible paths. Flex Logix has developed a DFT architecture that works well with eFPGA. In the latest generation of our EFLX eFPGA (Generation 2.4) we now have stuck-at (DC) coverage >98% and transition (AC) coverage >95%. We provide the test vectors for eFPGA test to achieve this coverage. Our coverage exceeds the requirements for some customers in which case we can “prune” our vectors to achieve whatever subset of coverage with lower test time.

Embedded in most eFPGAs are block RAMs which we fabricate using the foundry’s memory compilers. We provide data paths from the edge of the eFPGA to each block RAM so the SoC’s MBIST can test each RAM in the eFPGA array.

eFPGA test cost reduction

Once the DFT vectors are set to achieve a certain coverage, we focus on increasing scan time to run the vectors in the fewest milliseconds.

Let’s take an example since transistor speeds vary by node.

In N16, our Gen2.4 architecture improves our scan speed for test vectors from 50MHz in our earlier Gen2.0 design to 200MHz for Gen2.4. This is achieved, using lower power, by pipelining key portions of the scan circuitry in the EFLX eFPGA. A 4x faster scan speed means a 4x reduction in eFPGA test time and cost.

Another consideration is the number of GPIOs (in a pin-mux) that are used for test. Our new test architecture in Gen2.4 gives the customer the ability to tradeoff for fewer GPIOs or greater GPIOs. The fewer GPIO option is of interest to low-cost, low-pin-count products.

eFPGA is ready for prime time

Customers are using eFPGA for one of two reasons:

  1. Integrating an expensive and power-hungry FPGA into their own SoC for a 10x cost/power reduction.
  2. Adding eFPGA to their chip to give flexibility for changing standards, improving algorithms and customer optimization requests.

Having high DFT coverage and low test costs are critical for enabling the use of eFPGA in these applications. Learn more at flex-logix.com.

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