eFPGA As Fast And Dense As FPGA, On Any Process Node

How a key interconnect innovation helped make eFPGA economical across nodes.


A challenge for eFPGA when we started Flex Logix is that there are many customers and applications, and they all seemed to want eFPGA on different foundries, different nodes and different array sizes. And everyone wanted the eFPGA to be as fast and as dense as FPGA leaders’ on the same node. Oh, and customers seem to wait to the last minute then need the eFPGA ASAP.

Xilinx and Altera (Intel PSG now) take ~3 years and dozens or hundreds of people to bring out a new FPGA family in a new process node. How can Flex Logix develop eFPGA that is as fast and as dense in less than a year with a much smaller team?

Revolutionary FPGA interconnect

Flex Logix Co-Founder and Senior VP, Cheng Wang, designed multiple FPGA chips of increasing complexity while doing his PhD at UCLA. In the process he realized traditional mesh interconnect used in FPGAs takes up 80% of the area: the programmable logic was just 20%. So, he invented a new type of interconnect that is as good as mesh but can be implemented using half the transistors and half the metal layers!

Cheng, his Professor Dejan Markovic and others at UCLA presented a paper at ISSCC on this new interconnect used in their final FPGA project & won the prestigious Outstanding Paper Award. 3 out of 4 of them are involved with Flex Logix today.

UCLA filed a patent on the interconnect: Flex Logix is the exclusive licensee. Since founding Flex Logix, Cheng has made numerous improvements to the interconnect which are covered by Flex Logix patents. Flex Logix now has over 20 issued US patents and our first in China.

How we use our patented interconnect to design eFPGA

FPGA companies have very large design teams and take years because they do full-custom design, which is typically reserved for very large, high volume products including microprocessors.

eFPGA is needed across multiple foundries and dozens of nodes. If we had to hire 50+ people for each version, eFPGA could never be made economical or made available in a timely fashion.

Most ASIC designs today are done using standard cells: simple building blocks made available, typically at no cost, by the foundries and already characterized across process, voltage and temperature. Standard cell designs can be assembled following logic design rules and be guaranteed to work.

But standard cell designs typically are 2x the area of an optimized full custom design.

An FPGA is 80% interconnect and Cheng’s interconnect takes ½ the transistors. So instead of making our eFPGA smaller we make our eFPGA all from standard cells: the 2x area increase using standard cells is offset by the 50% area reduction of Cheng’s interconnect. So, we end up with about the same density and performance as FPGA leaders in a given process node.

But because we design using standard cells, we get to market in much less than a year from when we start. And with a much smaller design team.

So, if a customer wants eFPGA for a foundry/node we don’t have, from 180nm to 5nm, we can deliver quickly within their design schedule constraints.


eFPGA is valuable for accelerating critical workloads and making SoCs adaptable for changing algorithms and protocols. With Flex Logix’ revolutionary interconnect technology and design approach, we can make it available economically on any foundry/process node in less than a year.

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