Experts At The Table: Process Technology Challenges

First of three parts: migration from 28nm to 20nm; finFETs; equipment changes and complexity; the role of FD-SOI.


By Mark LaPedus
Semiconductor Manufacturing & Design sat down to discuss future transistor, process and manufacturing challenges with Subramani Kengeri, vice president of advanced technology architecture at GlobalFoundries; Carlos Mazure, chief technical officer at Soitec; Raj Jammy, senior vice president and general manager of the Semiconductor Group at Intermolecular; and Girish Dixit, vice president of the customer integration center at Lam Research. What follows are excerpts of that conversation.

SMD: From your vantage point, what are the near term challenges?

Kengeri: Right now, we are talking about moving from 28nm to 20nm. If you go back and look at the history, every generation had challenges. Recently, when I was giving a keynote at the ASMC conference, I asked the audience: ‘What do you think? Is it the technical challenges or is it the economic realities that are the biggest threat today?’ Unanimously, everyone said it was the economic realities. Every node transition is definitely a challenge and you have to look at it from at least four angles in our view. One is electrical scaling. There is physical scaling, cost scaling, and, of course, reliability. You specifically asked about the migration from 28nm to 20nm. In 28nm to 20nm, we know the whole industry stayed planar except for, of course, a big IDM, which elected to go with finFETs. The foundry world stayed on planar. That means we needed to address double patterning and things like that. The area shrink was there, but the cost is not necessarily scaling in the same way. There are tradeoffs and a combination of many things. At the end of the day, nobody has time to do so many process nodes. We have to cover a wide range of applications with potentially a single platform at 20nm. The other point is equipment readiness, EDA, and the rest of the ecosystem. You can have the technology ready, but if you don’t have the equipment or the design readiness at the same level, you will obviously fail.

Dixit: From an equipment perspective, the only common theme is change. But if I compare customers, there is more and more customization going on. There may be some other general statements we can make. The technology is getting complex, but this is nothing new. But the types of challenges that we see are very different from different customers. And again, it’s very specific to the types of geometries and the types of layouts. One thing that might be common to all of this is patterning schemes. They have been complicated. They are getting more and more complicated. You end up spending a lot of time just getting that right. And if you look at the end products, I don’t think there is one golden solution for everything. Just look at the benchmarks. Ten or 15 years ago, there was one or maybe two benchmarks. Now there are 10 different benchmarks. That in itself speaks to different performance metrics people are looking at. What is good for one application may not be necessarily good for something else. Going from 2D to 3D is also huge.

SMD: Speaking of 3D, what are the challenges going from planar transistors to finFETs?

Jammy: As I look at 28nm and 20nm, most of the world has stayed planar except for Intel, which has introduced finFET technology. But as we go very fast toward the 16nm and 14nm generations with finFET implementations, one concern I do have is many of our tools are geared for the planar world. We must ask ourselves this question: ‘For 3D architectures, are we prepared for the right kind of tooling in terms of putting the films down or the metrology that is needed and what we need to track?’ This even applies in terms of the EDA tools that are necessary to make this technology successful. That to me is a big challenge for finFETs. Even from the memory side, NAND flash is moving rapidly into the 3D space. Even there, a lot of it is being done on a 2D infrastructure base.

Kengeri: The finFET is challenging, but I don’t see it as an insurmountable challenge. For example, we have high-k/metal-gate. It’s a big issue, but we’ve solved the problem. Double patterning was a problem. Now, of course, there are a few other challenges. However, we have seen finFET silicon that is ahead of our plan. Again, finFET is not new to any of us. We’ve been working on it for over 10 ten years. It has been a matter of when we want to introduce it. Metrology is, of course, one of the biggest challenges. That is being addressed. We will solve the rest of the problems. Some of the key metrics are AC-DC targets. And of course, defect density and yield. And those metrics are ahead of our plan. So, we don’t see any real issues bringing finFETs into high-volume production.

SMD: For the initial finFETs, the foundries are combining a 14nm-class fin to a 20nm interconnect. What is the purpose behind that?

Kengeri: FinFET is risky and new. There are industry and business pressures for the foundry world to move to finFETs. But that doesn’t mean we are going to gamble and try to do something risky. And so, we said: ‘Let’s advance finFET first on the existing platform on the front end. Leave the middle-of-the-line and backend exactly the way they are, because there is a huge amount of learning there.’ For example, the investment that has gone into 20nm double patterning planar is huge. In other words, we will minimize the risk going from planar to finFETs. We are leveraging everything from 20nm planar at different levels. This is very compelling to customers. And the rest of the foundries are following us.

SMD: FD-SOI is starting at the 28nm node and will scale planar for three generations. What role does FD-SOI play in all of this?

Mazure: From a substrate point of view, we are basically addressing both approaches—the finFET 3D device as well the planar fully-depleted SOI device. In both cases, one shouldn’t take it as one against the other. There is space for both device architectures. It depends on the application and the circuits you are applying to them. FD-SOI planar is a fully depleted device, while the available 3D finFETs are actually doped. That has some advantages and disadvantages in terms of variability. With FD-SOI today—and the way it is being presented at the product level by STMicroelectronics and also shown by GlobalFoundries—the technology is suitable for mobile applications. Of course, for companies moving into the high-performance range with graphics processors and microprocessor, the 3D finFET may appear to be the technology of choice. In any case, we offer a solution for both.

Kengeri: So when looking at all of this, the FD-SOI and finFET come very, very close in terms of taking it to the next level. We are still offering both for certain specific reasons. There are some applications that can take full advantage of FD-SOI. It’s 28nm planar and a simpler process. There is a substrate overhead, which is, to some extent, offset by the simplicity of the process at two levels. One is the mask level itself. In addition, there is no need for complex stressors and things like that. Both finFETs and FD-SOI are fully depleted devices. At the end of the day, we are a foundry and customer-centric. We will leave it to the customer to choose whether they want to continue to extend planar and go with FD-SOI or switch over to finFET. Both have their own distinct advantages.

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